Intel MCS48 User Manual page 304

Family of single chip microcomputers
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8253/8253-5
MODE
0:
Interrupt
on
Terminal
Count
clock
jTjTJTjijrijTjxnjxnLJT_n_n_
WFfnHL—
F
4
1
3
1
2
l
1
1
OUTPUT
(INTERRUPT)
1
(n
=
4)
r
I
,
1
1
1
1
I
WRm
*~l
I
1
GAlb
S
J
1
3
2
1
1
4
1
OUTPUT
(INTERRUPT)
_l
MODE
3:
Square
Wave
Generator
clock
JTJTJTJTJTJTJTJTJTJTJTJ-LTL
4242424242424
OUTPUT
(n
=
4)
_J
1
I
1
I
1
f
~
OUTPUT
(n
=
5)
S4252S4252542
J
1
I
J"
MODE
1:
Programmable One-Shot
clock
JTJIJTJIJTJTJTJTJTJIJXriJI-
WRn~"
|
|
TRIGGER
|
OUTPUT
TRIGGER
_
OUTPUT
4
3
2
10
(n
=
4)
"L
4
3
2
4
3
2
10
MODE
4:
Software Triggered Strobe
clock
jxnjiJiJijTjTJijijnjTrLrL
OUTPUT
LOAD
n
"
GATE
OUTPUT
n =
4
r
4
3
2
10
t
r
4
3
2
10
MODE
2:
Rate Generator
cLocK_njTjxiXTTJTJTJTJTJTJTXLJTJTJT_
0(3)
OUTPUT
(n
=
31
"LJ
MODE
5:
Hardware
Triggered Strobe
clock
JTJIJIJTJTJIJIJTJTJTJXJ-LrL.
4
3
2
10
OUTPUT
(n
=
4)
OUTPUT
(n
=
4)
4
3
4
3
2
10
Figure
5.
8253 Timing Diagrams
8-14
00745A

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