Intel MCS48 User Manual page 281

8214
A.C.
CHARACTERISTICS
t a = o°c
to
+70°c,
v
cc
=
+5V ±5%
Parameter
Limits
Symbol
Min.
Typ.Ml
Max.
Unit
*CY
CLK
Cycle
Time 80
50
ns
tpw
CLK,
ECS,
INT
Pulse
Width 25 15
ns
tiss
INTE
Setup
Time
to
CLK
16 12 ns
tlSH
INTE Hold
Time
after
CLK
20 10
ns
tETCS
121
ETLG
Setup Time
to
CLK
25
12 ns
tETCHf
21
ETLG
Hold
Time
After
CLK
20
10 ns
tECCS
121
ECS
Setup
Time
to
CLK
80 25 ns
tECCH
131
ECS
Hold
Time
After
CLK
ns
tgCRS
131
ECS
Setup
Time
to
CLK
110
70
ns
tECRH
131
ECS
Hold
Time
After
CLK
t£CSS
l2]
ECS
Setup
Time
to
CLK
75
70
ns
*ECSH
121
ECS
Hold
Time
After
CLK
ns
t
DC
s
121
SGS
and
B^-B^
Setup
Time
to
CLK
70 50
ns
tDCH
121
SGS
and B^-B^ Hold
Time
After
CLK
ns
tRCS
[31 R~0-R7
Setup
Time
to
CLK
90 55
ns
tRCH
[3]
Ro-R~7
Hold Time
After
CLK
ns
tics
INT Setup
Time
to
CLK
55 35
ns
tci
CLK
to
INT
Propagation Delay
15 25
ns
tRIS
141 R0-R7 Setup
Time
to
fNT 10
ns
tRIH
l4]
FVR7
Hold
Time
After
INT 35
20
ns
*RA
R0-R7
to
A0-A2
Propagation
Delay
80 100
ns
*ELA
ELR
to
A
-A2 Propagation Delay
40 55
ns
*ECA
ECS
to
A0-A2
Propagation Delay
100 120
ns
*ETA
ETLG
to
A0-A2
Propagation Delay
35
70
ns
tDECS
141
SGS
and
B^-B^
Setup
Time
to
ECS
15 10
ns
tDECH t4]
SGS
and B^-§7 Hold
Time
After
ECS
15 10
ns
tREN
R^-R~7to
ENLG
Propagation Delay
45 70
ns
tETEN
ETLG
to
ENLG
Propagation Delay
20 25
ns
*ECRN
ECS
to
ENLG
Propagation Delay
85 90
ns
l ECSN
ECS
to
ENLG
Propagation Delay
35 55
ns
CAPACITANCE^
Parameter
Limits
Symbol
Min.
Typ.IU Max
Unit
C
IN
Input Capacitance
5
10 pF
CquT Output Capacitance
7 12 PF
Test Conditions:
V
B
|
AS
= 2.5V,
V
cc
=
5V,
T
A
= 25°C,
f
=
1
MHz
NOTE
5.
This parameter
is
periodically sampled and
not
100%
tested.
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