Intel MCS48 User Manual page 51

SINGLE
COMPONENT
SYSTEM
Designation
Pin*
Number
Function
V
Ss
V
DD
Vcc
PROG
P10-P17
(Port
1)
P20-P27
(Port 2)
D0-D7
(BUS)
20
26
40
25
27-34
21-24
35-38
12-19
TO
T1
INT
RD
39
6
8
Circuit
GND
potential
Programming power
supply;
+25V
during
program,
+ 5V
during operation
for
both
ROM
and
PROM. Low
power standby
pin
in
8048
ROM
version
Main power
supply;
+5V
during operation
and
8748 programming.
Program
pulse (+23V) input
pin
during
8748
programming.
Output
strobe
for
8243
I/O
expander.
8-bit
quasi-bidirectional port.
(Internal
Pullup
~ 50KH)
8-bit quasi-bidirectional port.
(Internal
Pullup
* 50KO)
P20-P23
contain the four high order
program
counter
bits
during
an
external
program
memory
fetch
and
serve
as a
4-bit
I/O
expander bus
for
8243.
True
bidirectional port
which can be
written
or read syn-
chronously using
the
RD,
WR
strobes.
The
port
can
also
be
statically latched.
Contains
the
8 low order
program
counter
bits
during
an
external
program
memory
fetch,
and
receive
s
the ad-
dressed
instruction
under
the control of
PSEN.
Also con-
tains
the
address and
data during
an
external
RAM
data
store instruction,
under
control of
ALE, RD, and
WR.
Input pin testable using the conditional transfer
instruc-
tions
JTO and JNTO.
TO
can be
designated as a
clock
output using
ENTO CLK
instruction.
TO
is
also
used
dur-
ing
programming.
Input pin testable
using the JT1,
and
JNT1
instructions.
Can
be
designated the event counter
input using the
STRT CNT
instruction.
Interrupt input. Initiates
an
interrupt
if
interrupt
is
enabled.
Interrupt
is
disabled
after
a
reset. (Active low)
Output strobe activated during a
BUS
read.
Can
be
used
to
enable data onto
the
BUS
from an
external
device. (Active low)
Used
as a
Read
Strobe
to
External
Data Memory.
*8048, 8748,
8049
2-15