Intel MCS48 User Manual page 293

8251
A
When
used
as
an
input (external
SYNC
detect
mode),
a
positive going signal will
cause the
8251
A
to
start
assem-
bling
data characters
on
the
rising
edge
of the
next RxC.
Once
in
SYNC,
the
"high" input
signal
can be removed.
When
External
SYNC
Detect
is
programmed,
the Internal
SYNC
Detect
is
disabled.
BREAK DETECT
(Async
Mode
Only)
This output
will
go high
whenever
the receiver
remains
low
through
two
consecutive stop
bit
sequences (including the
start
bits,
data
bits,
and
parity
bits).
Break Detect
may
also
be read
as a
Status
bit.
It is
reset
only
upon
a
master chip
Reset or
Rx
Data returning to
a
"one"
state.
ADDRESS
BUS
CONTROL BUS
I/O
R
I/O
W
RESET
7S
\7
C/D
CS~
D,-D„
RD WR RESET CLK
Figure
4.
8251
A
Interface to
8080 Standard
System Bus
DETAILED
OPERATION
DESCRIPTION
General
The
complete
functional definition of the
8251
A
is
pro-
grammed
by
the system's software.
A
set
of control
words
must be
sent
out by
the
CPU
to
initialize
the
8251
A
to
support the
desired
communications
format.
These
control
words
will
program
the:
BAUD
RATE,
CHARACTER
LENGTH,
NUMBER
OF STOP
BITS,
SYNCHRONOUS
or
ASYNCHRONOUS
OPERATION, EVEN/ODD/OFF
PAR-
ITY,
etc. In
the
Synchronous Mode,
options
are also pro-
vided to
select either internal or external character synchro-
nization.
Once programmed,
the
8251
A
is
ready
to
perform
its
com-
munication functions.
The
TxRDY
output
is
raised
"high"
to signal the
CPU
that the
8251
A
is
ready to
receive
a
data
character
from
the
CPU.
This output
(TxRDY)
is
reset
automatically
when
the
CPU
writes
a
character into the
8251
A.
On
the other hand, the 8251
A
receives
serial
data
from
the
MODEM
or I/O device.
Upon
receiving an entire
character, the
RxRDY
output
is
raised
"high"
to
signal
the
CPU
that the 8251
A
has
a
complete
character ready
for
the
CPU
to
fetch.
RxRDY
is
reset
automatically
upon
the
CPU
data read operation.
The 8251
A
cannot begin transmission
until
the
Tx Enable
(Transmitter Enable)
bit
is
set in
the
Com mand
Instruction
and
it
has received
a
Clear
To Send
(CTS)
input.
TneTxD
output
will
be held
in
the
marking
state
upon
Reset.
Programming
the 8251
A
Prior to starting
data transmission or reception, the
8251A
must
be loaded with
a set
of control
words generated by
the
CPU. These
control signals
define the
complete
func-
tional
definition of the
8251A
and must immediately
fol-
low
a
Reset operation
(internal
or external).
The
control
words
are
split
into
two
formats:
1.
Mode
Instruction
2.
Command
Instruction
Mode
Instruction
This format defines the general operational
characteristics
of the
8251
A.
It
must
follow
a
Reset operation
(internal or
external).
Once
the
Mode
Instruction has
been
written into
the
8251A
by
the
CPU,
SYNC
characters or
Command
In-
structions
may
be inserted.
Command
Instruction
This
format
defines
a status
word
that
is
used to control the
actual
operation of the
8251
A.
Both
the
Mode
and
Command
Instructions
must conform
to
a
specified sequence for proper device operation.
The
Mode
Instruction
must
be
inserted
immediately following
a
Reset operation, prior to using the
8251
A
for data
com-
munication.
All control
words
written into the
8251
A
after the
Mode
In-
struction will
load the
Command
Instruction.
Command
Instructions
can be written into the
8251
A
at
any time
in
the data block during the operation of the
8251
A.
To
re-
turn to the
Mode
Instruction
format, the master Reset
bit
in
the
Command
Instruction
word
can be
set
to
initiate
an
internal
Reset operation
which
automatically
places the
8251
A
back
into the
Mode
Instruction format.
Command
Instructions
must
follow the
Mode
Instructions or
Sync
characters.
C/D '
1
MODE
INSTRUCTION
C/D =
1
SYNC
CHARACTER
1
C/D
-
1
SYNC CHARACTER
2
C/D =
1
COMMAND
INSTRUCTION
C/D
=
;
DATA
;
C/D =
1
COMMAND
INSTRUCTION
C/D
-
;
;
DATA
'.
C/D =
1
COMMAND
INSTRUCTION
The
second
SYNC
character
is
skipped
if
MODE
instruction
has
programmed
the
8251A
to single character Internal
SYNC
Mode. Both
SYNC
characters are skipped
if
MODE
instruction
has
programmed
the
8251A
to
ASYNC
mode.
Figure
5.
Typical
Data Block
8-3
0021
6A