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8291
B3
—
Enable
Active
Low
Interrupt:
Setting
this
bit
causes
the
polarity of
the
INT
pin to
be
reversed, providing
an
output
signal
compatible
with
Intel's
MCS-48™.
Interrupt
registers
are not affected
by
this
bit.
PARALLEL POLL
PROTOCOL
Writing a
OHUSP3P2P1
into
the Auxiliary
Mode
Register
will
configure (U=0)
or
unconfigure (U=1
)
the 8291
for
a
parallel
poll.
When
U=0,
this
command
is
the
"Ipe"
(local
poll
enable)
local
message
as defined
in
IEEE
488.
The
"S"
bit
is
the
sense
in
which
the 8291
is
configured; only
if
the
Parallel Poll
Flag
("ist"
local
message) matches
this
bit will
the
Parallel Poll
Response, PPRn, be
sent
true.
The
bits
P3P2P1
specify
which
of
the eight data
lines
PPRn
will
be
sent
over.
Thus,
once
the
8291 has
been
configured
for
Parallel
Poll,
whenever
it
senses both EOI
and
ATN
true,
it
will
automatically
compare
its
PP
flag
with the
sense
bit
and send
PPRn
true or
false
according
to
the
comparison.
If
a
PP2* implementation
is
desired, the "Ipe"
and
"ist"
local
messages
are
all
that
are
needed.
Typically,
the user
will
configure the 8291
for Parallel Poll
immediately
after
initialization.
During
normal
operation
the
micro-
processor
will
set or clear
the
Parallel Poll
Flag
(ist)
according
to
the device's
need
for service.
Consequently
the 8291
will
be
set
up
to
give the
proper response
to
IDY
(EOI
•
ATN)
without
directly
involving the
micropro-
cessor.
If
a
PP1* implementation
is
desired,
the
undefined
command
features
of
the 8291
must
be
used.
In
PP1, the
8291
is
indirectly
configured
for Parallel Poll
by
the
active
controller
on
the
GPIB.
The sequence
at
the 8291 being
configured
is
as
follows:
1.
The
PPC
message
is
received
true.
Being an undefined
command,
it
is
loaded
into
the
Command
Pass
Through
Register,
and
a
CPT
interrupt
is
sent
to
the
microprocessor.
The handshake
is
automatically held
off.
2.
The
microprocessor
reads the
CPT
Register
and sends
VSCMD
to
the 8291, releasing the
handshake.
3.
Having
received
an undefined primary
command,
the
8291
is
set
up
to
receive
an undefined
secondary
command,
the
PPE
message.
This
message
is
also
received
into
the
CPT
Register, the
handshake
is
held
off,
and
the
CPT
interrupt
is
generated.
4.
The
microprocessor
reads the
PPE
message
and
decodes
the
SP3P2P1
information.
It
then
sends
the
appropriate
"Ipe"
local
message
to
the
8291
.
Finally,
the
microprocessor sends
VSCMD
and
the
handshake
is
released.
*As defined
in
IEEE Standard
488.
End
of
Sequence (EOS)
Register
EC7
EC6
EC5
EC4
EC3
EC2
EC1
ECO
EOS REGISTER
The
EOS
Register
and
its
features
offer
an
alternative
to
the
"Send EOI"
auxiliary
command. A
seven
or eight
bit
byte (ASCII or
binary)
may
be placed
in
the
register to
flag
the
end
of
a
block
or read.
The
type
of
EOS
byte
to
be used
is
selected
in
Auxiliary
Register
bit
A4.
If
the 8291
is
a
listener,
and
the
"End on
EOS
Received"
is
enabled
at
bit
A2,
then an
End
interrupt
is
generated
in
the
Interrupt
Status
1
Register
whenever
the byte
in
the Data-
in
Register
matches
the byte
in
the
EOS
Register.
If
the 8291
is
a
talker,
and
the
"Output EOI on
EOS
Sent"
is
enabled
at
bit
A3,
then the
EOI
line
is
sent true with the
next data byte
whenever
the
contents
of
the
Data
Out
Register
match
the
EOS
register.
Reset Procedure
The
8291
is
reset to
an
initialization
state either
by a
pulse applied
to
its
Reset
pin,
or
by
a
reset auxiliary
command
(02H
written
into
the
Auxiliary
Command
Register).
The
following conditions are
caused
by a
reset
pulse
(or
local
reset
command):
1
.
A
"pon"
local
message
as defined by
IEEE 488
is
held
true
until
the
initialization
state
is
released.
2.
The
Interrupt
Status Registers
are cleared.
3.
Auxiliary
Registers
A
and
B
are cleared.
4.
The
Serial Poll
Mode
Register
is
cleared.
5.
The
Parallel Poll
Flag
is
cleared.
6.
The
EOI
bit in
the
Address
Status Register
is
cleared.
7.
N
F
in
the
Internal
Counter
is
set to
8
MHz.
This
set-
ting
causes
the longest possible
t-i
delay
to
be
generated
in
the
Source
Handshake
(16
^sec
for
1
MHz
clock).
The
initiallization
state
is
released
by an "immediate
execute pon"
command
(00H
written
into
the Auxiliary
Command
Register).
The
suggested
initialization
sequence
is:
1.
Apply
a
reset
pulse
or
send
the
reset
auxiliary
command.
2.
Set the desired
initial
conditions by
writing
into
the
Interrupt
Mask,
Serial
Poll
Mode, Address Mode,
Address
0/1
,
and
EOS
Registers. Auxiliary
Registers
A
and
B,
and
the
internal
counter should
also
be
initialized.
3.
Send
the
"immediate execute pon"
auxiliary
command
to
release the
initialization state.
4.
If
a
PP2
Parallel Poll
implementation
is
to
be used
the
"Ipe"
local
message
may
be
sent,
configuring the 8291
for
a
Parallel Poll
Response on
an assigned
line.
(Refer
to
the section
on
Parallel Poll
Protocol.)
8-97
00229A
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