Intel MCS48 User Manual page 264

8205
FUNCTIONAL
DESCRIPTION
Decoder
The 8205
contains
a
one
out of eight binary decoder.
It
ac-
cepts
a
three
bit
binary code and by
gating
this
input, creates
an exclusive output
that represents the value of the input
code.
For example,
if
a
binary code
of 101
was
present
on
the
A0,
A1
and
A2
address input
lines,
and
the device
was
enabled,
an
active
low
signal
would
appear
on
the
05 output
line.
Note
that
all
of the other output
pins are
sitting at a logic
high, thus the decoded output
is
said
to be exclusive.
The
decoders outputs
will
follow the
truth table
shown
below
in
the
same manner
for
all
other input
variations.
Enable Gate
When
using
a
decoder
it is
often necessary to gate the out-
puts
with timing
or enabling
signals
so that the exclusive
output
of the decoded
value
is
synchronous
with the
overall
system.
The 8205
has
a built-in
function
for
such
gating.
The
three
enable inputs (El, E2, E3)
are
ANDed
together and create
a single
enable
signal for the decoder.
The
combination
of
both
active
"high" and
active
"low"
device enable inputs
provides the designer with
a
powerfully
flexible
gating func-
tion to help reduce package count
in his
system.
ENABLE GATE
£>
ADDRESS
ENABLE OUTPUTS
A
A,
A
2
El
E
2
E
3
1
2 3 4 5 6
7
L L
L
L L
H
L
H H H H H H H
H
L
L
L
L
H H
L
H H H H H H
L
H
L L L
H H
H
L
H H H H H
H H
L L L
H
H
H H
L
H
H
H H
L
L
H
L
L
H H H
H
H
L
H H H
H
L
H
L
L
H H H H H H
L
H H
L
H
H
L L
H H H H
H H
H
L
H
H H H
L L
H H
H
H H H H H
L
XXX
L L L
H H H H H H H H
XXX
H
L L
H H H
H
H H H H
XXX
L
H
L
H
H H
H H
H
H H XXX
H H
L
H H H H H H H H
XXX
H
L
H H H H
H
H H H H
XXX
L
H
H H
H
H
H H H H H
XXX
H H H H H
H
H
H
H H H
7-26