Intel MCS48 User Manual page 297

8251
A
Other Timings:
SYMBOL PARAMETER
MIN.
MAX.
UNIT
TEST CONDITIONS
tCY
Clock
Period
320 1350
ns Notes
5,
6
H Clock High
Pulse
Width
140 tCY-90
ns
tff
Clock
Low
Pulse
Width
90
ns
tR.tp
Clock
Rise
and
Fall
Time
5 20
ns
tDTx
TxD
Delay from
Falling
Edge
of
TxC
1
Ms
tSRx
Rx
Data Set-Up Time
to
Sampling
Pulse 2
Ms
tHRx
Rx
Data
Hold Time
to
Sampling
Pulse
2
Ms
fTx Transmitter Input Clock Frequency
1x
Baud
Rate
DC
64 kHz
16x Baud Rate
DC
310 kHz
64x Baud
Rate
DC
615 kHz
tTPW
Transmitter Input Clock
Pulse
Width
1x Baud Rate
12
*CY
16x and 64x Baud Rate
1 *CY
*TPD
Transmitter Input Clock
Pulse
Delay
1x Baud Rate
15
*CY
16xand
64x Baud
Rate 3
*CY
fRx
Receiver Input Clock Frequency
1x
Baud
Rate
DC
64
kHz
16x Baud
Rate
DC
310 kHz
64x Baud
Rate
DC
615 kHz
tRPW Receiver Input
Clock Pulse Width
1x Baud
Rate
12
*CY
16x and 64x Baud
Rate
1
tCY
*RPD
Receiver Input
Clock Pulse Delay
1x
Baud
Rate
15
*CY
16x and 64x Baud
Rate
3
*CY
tTxRDY
TxRDY
Pin Delay from Center
of
last
Bit 8
*CY
Note
7
*TxRDY CLEAR
TxRDY
|
from
Leading Edge
of
WR
180
ns
Note
7
tRxRDY
RxRDY
Pin
Delay from
Center
of
last Bit
24
*CY
Note
7
tR
x
RDY
CLEAR
RxRDY
4-
from
Leading
Edge
of
RD
150
ns
Note
7
tis
Internal
SYNDET
Delay from
Rising
Edge
of
RxC
24
*CY
Note
7
tES
External
SYNDET
Set-Up Time
Before
Falling
Edge
of
RxC
16
tCY
Note
7
tTxEMPTY
TxEMPTY
Delay
from
Center
of Last
Bit
20
*CY
Note
7
*WC
Control Delay
from
Rising
Edge
of
WRITE
(TxEn,DTR, RTS)
8
tCY
Note
7
tCR
Control
to
READ
Set-Up
Time
(DSR, CTS)
20
tCY
Note
7
5.
The
TxC
and
RxC
frequencies have the following
limitations
with
respect to
CLK.
For 1x Baud
Rate
,
fj
x or
f
Rx
**
1/(30
tcY>
For 16x and 64x Baud Rate,
f-|-
x
or
fp
x
<
1/(4.5
\q,\)
6.
Reset Pulse
Width = 6
t CY
minimum;
System Clock must
be running during Reset.
7.
Status
update can have
a
maximum
delay of
28
clock periods from
the
event
affecting the
status.
8-7 0021
6A