Intel MCS48 User Manual page 352

intel
8278
PROGRAMMABLE KEYBOARD
INTERFACE
Simultaneous Keyboard and
Display
Operations
Interface
Signals
for
Contact and
Capacitive
Coupled Keyboards
128-Key Scanning
Logic
10.7
msec
Matrix
Scan Time
for
128
Keys and
6
MHz
Clock
8-Character
Keyboard FIFO
N-Key
Rollover with
Programmable
Error
Mode
on
Multiple
New
Closures
16-Character
7-Segment
Display
Interface
Right or
Left
Entry Display
RAM
Depress/Release
Mode
Programmable
Interrupt
Output on Key
Entry
The
Intel®
8278
is
a general
purpose programmable keyboard and
display interface device designed
for
use
with
8-bit
microprocessors such
the
MDS-80™
and
MCS-85™. The
keyboard
portion
can
provide a
scanned
interface to
128-key contact or capacitive-coupled keyboards.
The
keys
are
fully
debounced
with N-key rollover
and
programmable
error generation
on
multiple
new
key
closures.
Keyboard
entries are
stored
in
an
8-character
FIFO
with overrun status indication
when
more
than 8 characters
are entered.
Key
entries set
an
interrupt
request output
to
the
master CPU.
The
display portion
of
the
8278
provides a
scanned
display interface for
LED, incandescent, and
other
popular display technologies. Both numeric displays
and
simple
indicators
may
be
used.
The
8278 has a
16X4
display
RAM
which can
be loaded or interrogated
by the
CPU.
Both
right
entry calculator
and
left
en-
try
typewriter display formats
are possible.
Both read
and
write of the display
RAM
can be
done
with auto-
increment
of the display
RAM
address.
PIN
CONFIGURATION
PIN
NAMES BLOCK DIAGRAM
RLC
y
40
Dvcc
xi
C
2 39
UCLR
X2\2
3 38
HB3
RESET
C
4 37
Db
2
NCC
5
36
Hb,
CSC
6
35
Hbo
gndC
34
Dkcl
rdC
8 33
]M
6
AoC
9 32
3m
5
WR C
SYNCC
10 31
8278
11 30
Dm
4
3m
3
DoC
12 29
Hm
2
D,[I 13 28
Dm,
D
2
C
14 27
Dm
D
3
C
15 26
DVdd
D«C
16 25
Dnc
D
5
C
17
24
3 ERROR
DeL
18
23
DlRQ
D7C
19 22
Dhys
gndC
20
21
Dbp
D
7
-D
DATA BUS
RD.WR
READ, WRITE
STROBES
CS CHIP
SELECT
Ao
CONTROL/DATA SELECT
RESET RESET INPUT
X,,X
2
FREQ.
REFERENCE INPUT
SYNC HIGH
FREQUENCY OUTPUT
CLOCK
RL
KEYBOARD RETURN
LINE
CLR
CLEAR ERROR
KCL KEY CLOCK
M
6
-M
MATRIX SCAN LINES
DISPLAY
OUTPUTS
ERROR ERROR
SIGNAL
IRQ
INTERRUPT REQUEST
HYS HYSTERESIS
BP
TONE ENABLE
i<»
DATA
BUS
BUFFER
REGISTER
n
O
—
I/O
y1_K
-.
CONTROL
C
>
1
nfiir
NTT'
TT
O
r
H
o
n
CO
-HYSTERESIS
-KEY CLOCK
.SYNC
(400
KHz)
TONE ENABLE
ERROR OUTPUT
CLEAR INPUT
<0
16-DIGIT
A N TO
"
>
DISPLAY
BUFFER
v
""
DIGITS
PWR-
GND-
INTEl
CORPORATION ASSUMES NO
RESPONSIBILITY FOR
THE USE OF ANY CIRCUITRY
OTHER THAN CIRCUITRY EMBODIED IN
AN INTEL PRODUCT.
NO
OTHER CIRCUIT
PATENT
LICENSES
ARE
IMPLIED.
©
INTEL
CORPORATION, 1979
g.g2
00227A