Intel MCS48 User Manual page 60

SINGLE
COMPONENT
SYSTEM
X
ADDRESS
/
C0DE /
XDATA \/
DATA OUT
(P20-P23)
X
ADDRESS
Y^
,
C0DE
A
DATA
OUT
PORT
ADDRESS
BITS
2,3
READ
WRITE
PORT
2
FOR
EXPANDED
I/O
WITH
8243
FIGURE
6.
EXPANDED
I/O
TIMING
DIAGRAM
2.10
CPU
The
8021
CPU
has
arithmetic
and
logical
capability.
A
wide
variety of arithmetic
and
logic instructions
may
be
exercised,
which
affect
the contents
of
the accumulator,
and/or
direct
or
indirect
scratchpad
loca-
tions.
Provisions have been
made
for
simplified
BCD
arithmetic capability using
the
DAA,
SWAP
A,
and
XCHD
instructions.
In
addition,
MOVP
A,@A
allows table
lookup
for
display
formating and
constants.
The
conditional branch
logic within the
processor enables
several
conditions
inter-
nal
and
external
to
the processor
to
be
tested by the users program.
Use
the
conditional
jump
instructions with the
tests
listed
below
to effect a
change
in
the
program
execution sequence.
Test
Jump Jump
Condition Instructions
Accumulator
A=0 A*0 JZ
JNZ
Carry
Flag
1
JNC, JC
Timer Overflow
Flag
—
1
JTF
Test lnput-T1
1
JNT1,
JT1
2.11
Reset
A
positive-going signal
to
the
RESET
input
resets
the necessary miscellaneous
flip-
flops
and
sets
the
program
counter
and
stack pointer
to zero.
2-24