Intel MCS48 User Manual page 72

Family of single chip microcomputers
Hide thumbs Also See for MCS48:
Table of Contents

Advertisement

EXPANDED
MCS-48
SYSTEM
fore,
the
RD
and
WR
outputs
of
the
8048
are
required.
See
the following section
on
data
memory
expansion
for
more
detail.
The
sub-
sequent
section
on
I/O
expansion
explains
the operation
of
the 16
I/O
lines.
ALE
PSEN
WR
8048
rd
BUS
P20-P23
12
u
\>
TEST
I/O
INPUTS
ALE
2K
X
8
RD
IOW
l0R
ROM/
PROM
/
L
-S-
J
\
*/„
W,TH
C
8>
A/D
Q
_
7
|/o
N
V
8355/
8755
y/
A
8'
A
1C
cs
<x>
I/O
EXTERNAL
PROGRAM MEMORY
INTERFACE
3.2
Expansion
of
Data
Memory
Data
Memory
is
expanded beyond
the
resi
dent 64
words
by
using the
8085
type
bus
feature
of
the
MCS-48.
3.2.1
Read/Write Cycle
All
address and data
is
transferred
over
the
8
lines of
BUS.
A
read
or
write
cycle
occurs as
follows:
1.
The
contents
of register
R0
or
R1
is
out-
puted
on
BUS.
2.
Address
Latch
Enable (ALE)
indicates
address
is
valid.
The
trailing
edge
of
ALE
is
used
to latch
the
address
externally.
3.
A
read (RD)
or
write
(WR)
pulse
on
the
corresponding output
pins
of
the
8048
indi-
cates the type
of
data
memory
access
in
progress.
Output data
is
valid at
the
trailing
edge
of
WR
and
input
data
must be
valid at
the
trailing
edge
of
RD.
4.
Data
(8-bits)
is
transferred
in
or out
over
BUS.
READ
FROM
EXTERNAL DATA
MEMORY
ALE
J
L
RD
BUS
FLOATINgSAdDRESsY
yC
DATA
/\
FLOATING
FLOATING
WRITE
TO EXTERNAL DATA
MEMORY
ALE
J
1_
WR
BUS
FLOATING^ADDRESSyFLQATING^
DATA
J^
FLOATING
3-4

Advertisement

Table of Contents
loading

Table of Contents