Table of Contents
Advertisement
EM2
40-PIN
SOCKET CONFIGURATION
EM2 BLOCK DIAGRAM
P26
C
1
P27
C
2
AVcc
C
3
Varef
C
4
AN1
C
5
ANO
C
6
AVss
C
7
TO
C
8
Vth
C
9
POO
C
1<
P01
C
1'
P02
C
i:
P03
C
i:
P04
C
1'
P05
C
1!
P06
C
1<
P07
C
i;
ALE
C
H
T1 [I
1«
Vss
C
2C
EM2
31
TOP VIEW
30
3
v cc
3
P25
U
P24
3
prog
D
P23
3
P22
U
P21
U
P20
3
P17
H
P16
HP15
3
P14
H
P13
3
P12
H
pn
ZJP10
3
RESET
D
XTAL2
^
XTAL1
3
SUBST
CLOCK
64
WORDS
DATA
MEMORY
2048
EPROM
MEMORY
I
I
O
8-BIT
CPU
A
I
I
(,—
\
<>
O
8-BIT
TIMER-EVENT
COUNTER
/lJ
26
DIGITAL
I/O
LINES
TWO
CHANNEL
8-BIT
A/D
CONVERTER
V
8755A
\l
8022
EMULATOR
CHIP
U
PIN
1
SQUARE SOLDER
PAD
PIN
DESCRIPTION
Desig-
nation
Pin#
Function
V
ss
20
Circuit
GND
potential.
Vcc
4
+5V
circuit
power
supply.
PROG
37
Output
strobe
for Intel®
8243
I/O
ex-
pander.
P00-P07
10-17
8-bit
open-drain
port
with
comparator
Port
inputs.
The
switching threshold
is
set
externally
by
V
TH
.
Optional
pull-up
re-
sistors
may
be
added
via
ROM
mask
selection.
(The
emulator board
has
switch
selection
of this option.)
V
TH
9
Port
threshold reference
pin.
P10-P17 25-32
8-bit
quasi-bidirectional
port.
Port
1
P20-P27 33-36
8-bit
quasi-bidirectional
port.
Port 2
38-39
P20-P23
also serve
as a
4-bit I/O
ex-
1-2
pander
for Intel®
8243.
TO
8
Interrupt input
and
input pin testable
using the conditional
transfer
instruc-
tions
JT0 and JNT0.
Initiates
an
inter-
rupt
following
a low
level
input
if
inter-
rupt
is
enabled.
Interrupt
is
disabled
after
a
reset.
T1
19
Input pin testable
using the JT1
and
JNT1
conditional transfer instructions.
Can
be designated
the
timer/event
counter
input
using the
STRT
CNT
in-
struction.
Also serves as
the zero-cross
detection input
to
allow zero-crossover
sensing
of
slowly
moving
AC
inputs.
Optional
pull-up resistor
may
be
added
via
ROM
mask
selection.
Desig-
nation
Pin#
Function
RESET
AVc
AV
f
ANO,
AN1
ALE
XTAL1
XTAL2
24
Input
used
to
initialize
the
processor
by
clearing status
flip-flops
and
setting
the
program
counter
to zero.
7
A/D
converter
GND
potential.
Also
establishes the lower
limit
of
the con-
version range.
3
A/D
+
5V power
supply.
SUBST
21
Substrate
pin
used
with
a
bypass
capa-
citor to stabilize
the substrate voltage
and improve A/D
accuracy.
V
ARE
f
4
A/D
converter reference
voltage. Estab-
lishes
the
upper
limit
of
the
conversion
range.
6,5
Analog
inputs
to
A/D
converter.
Soft-
ware
selectable on-chip
via
SEL ANO
andSELAM
instructions.
18
Address
Latch Enable. Signal occur-
ring
once
every
30
input input
clocks
(once every
single cycle
instruction),
used
as an output
clock.
22
One
side
of crystal,
inductor, or
re-
sistor input for internal oscillator.
Also
input
for
external
frequency
source.
(Not
TTL
compatible.)
23
Other
side
of
timing
control
element.
This
pin
is
not
connected
when
an
ex-
ternal
frequency source
is
used.
9-24
Advertisement
Chapters
Table of Contents
