Intel MCS48 User Manual page 386

8291
INTERNAL
COUNTER
The
internal counter determines
the delay time allowed
for
the
settling of data
on
the
DIO
lines.
This delay time
is
defined as
1^ in
IEEE 488 and appears
in
the
Source
Handshake
state
diagram between
SDYS
and STRS. As
such,
DAV
is
asserted
T, after the
DIO
lines are driven.
Consequently,
T-i
is
a
major
factor
in
determining
the
data
transfer
rate
of
the 8291 over the
GPIB
(T
1
= TWROV2-TWROI5).
When
open-collector transceivers
are
used
for
connection
to the
GPIB,
Ti
is
defined by IEEE 488
to
be
2^sec.
By
writing
0010FFFF
into the Auxiliary
Mode
Register,
the
counter
is
preset
to
match
a
fc
MHz
clock
input,
where
FFFF
is
the binary
representation
of
Nf
(1<Nf<8,
Nf=(FFFF)
2
).
When Nf =
fc,
a 2/usec Ti delay
will
be
generated before each
DAV
asserted.
2N
F
M(Msec)=
j-
+*SYNC
>
1<N
F
<8
tSYNC
is
a synchronization
error,
greater than zero and
smaller than the
larger of
T
clock high
and T
clock
low.
(For a
50%
duty cycle
clock,
tsYNC
is
less
than
half
the
clock
cycle).
If it
is
necessary
that
Ti
be
different
from
2jusec,
Nf
may
be
set to a value other than
fc. In this
manner,
data transfer
rates
may
be
programmed
for
a given system.
In
small
systems,
for
example, where
transfer rates
exceeding
GPIB
specifications are required, one
may
set
Nf
<
fc
and
decrease
Ti.
When
tri-state transceivers are used,
IEEE 488
allows a
higher
transfer
rate
(lower Ti
).
Use
of the 8291 with
such
transceivers
is
enabled by
setting
B2
in
Auxiliary Register
B.ln
this
case, setting Nf
=
fc
causes
a Ti delay
of 2/xsec to
be generated
for the
first
byte transmitted
—
all
subsequent
bytes
will
have
a delay of
500
nsec.
Nf
Ti(High Speed)
^usec
=
~
+
tsYNC
2tc
Thus,
setting
N
F
=
1
using a 4
MHz
clock
will
generate
for a
50%
duty cycle clock
(t SYN
c
<125
nsec):
1-^=
-yj-
+
0.125
=
0.250
Msec
=
250 nsec
AUXILIARY REGISTER A
Auxiliary Register
A
is
a "hidden"
5-bit register
which
is
used
to
enable
some
of
the 8291
features.
Whenever
a
100
A4A3A2A1A0
byte
is
written
intothe Auxiliary
Register,
it
is
loaded
with the data A4A3A2A1A0.
Setting the
respective
bits
to "1"
enables
the following
features:
Ao
—
RFD/DAV
Holdoff
on
all
Data:
If
the 8291
is
listening,
RFD
will
not be
sent true
until
the
"finish
handshake"
auxiliary
command
is
issued
by
the microprocessor.
If
the
8291
is
talking,
DAV
is
not sent
true
until
the
"finish
handshake"
command
is
given.
In
both cases, the holdoff
will
be
in
effect for
each
data
byte.
A1
—
RFD/DAV
Holdoff
on
End: This
feature
enables the
holdoff
on EOI
or
EOS
(if
enabled).
However, no
holdoff
will
be
in
effect
on any other data
bytes.
A2
—
End
on
EOS
Received:
Whenever
the byte
in
the
Data
In
Register
matches
the byte
in
the
EOS
Register, the
End
interrupt
bit will
be
set
in
the
Interrupt Status
1
Register.
A3
—
Output EOI on
EOS
Sent:
Any
occurrence
of
data
in
the Data Out
Register
matching
the
EOS
Register causes
the EOI
line to
be
sent true along with the
data.
A4
—
EOS
Binary
Compare:
Setting
this
bit
causes the
EOS
Register
to function as a
full
8-bit
word.
When
it is
not
set,
the
EOS
Register
is
a
7-bit
word
(for
ASCII
characters).
If
Ao
=
A1
=
1
,
a special "continuous Acceptor Handshake
cycling"
mode
is
enabled. This
mode
should be used only
in
a controller system
configuration,
where
both the 8291
and
the 8292
are used.
It
provides
a
continuous
cycling
through
the Acceptor Handshake
state
diagram, requiring
no
local
messages
from
the microprocessor; the rdy
local
message
is
automatically generated
when
in
ANRS.
As
such,
the 8291 Acceptor
Handshake
serves as the
controller Acceptor Handshake.
Thus,
the controller
cycles through
the
Acceptor Handshake
without delaying
the data
transfer
in
progress.
When
the tcs
local
message
is
executed, the 8291
is
taken out
of
the "continuous
AH
cycling" mode,
the
GPIB
hangs up
in
ANRS,
and
a Bl
interrupt
is
generated
to indicate that control
may
be
taken.
A
simpler procedure
may
be used
when
a "tcs
on
end
of block"
is
executed;
the 8291
may
stay
in
"continuous
AH
cycling".
Upon
the end
of a
block (EOI or
EOS
received), a holdoff
is
generated, the
GPIB
hangs up
in
ANRS,
and
control
may
be taken.
AUXILIARY REGISTER
B
Auxiliary Register B
is
a "hidden"
4-bit register
which
is
used
to
enable
some
of
the features
of
the
8291
.
Whenever
a
IOIOB3B2B1B0
is
written
into
the Auxiliary
Mode
Register,
it
is
loaded with the data B3B2B1B0.
Setting the
respective
bits
to "1"
enables
the following
features:
Bo
—
Enable Undefined
Command
Pass Through: This
feature allows any
commands
not recognized by the 8291
to
be handled
in
software.
If
enabled,
this feature
will
cause
the 8291
to holdoff the
handshake when
an
undefined
command
is
received.
The
microprocessor
must
then read the
command
from
the
Command
Pass
Through
Register
and send
the
VSCMD
auxiliary
command.
Until
the
VSCMD
command
is
sent, the
handshake
holdoff
will
be
in effect.
B1
—
Send EOI
in
SPAS:
This
bit
enables
EOI
to
be sent
with the status
byte;
EOI
is
sent true
in
Serial Poll Active
State.
Otherwise, EOI
is
sent
false
in
SPAS.
B2
—
Enable High Speed
Data
Transfer: This
feature
may-
be enabled
when
tri-state external transceivers are used.
The
data
transfer
rate
is
limited by
Ti (delay
time
generated
in
the
Source
Handshake
function),
which
is
defined
according
to the type
of transceivers used.
When
the "High Speed"
feature
is
enabled,
Ti
=
2
microseconds
is
generated
for
the
first
byte transmitted
after
each
true to
false transition of
ATN.
For
all
subsequent
bytes, Ti
=
500
nanoseconds.
Refer
to the Internal
Counter
section
for
an
explanation
of Ti duration as a function
of
B2 and
of
clock
frequency.
8-96
00229A