Intel MCS48 User Manual page 187

8021
PIN
DESCRIPTION
Designation
Pin
#
Function
Vss
Vcc
PROG
P00-P07
PortO
P10-P17
Port
1
P20-P23
Port 2
T1
14
Circuit
GND
potential
28
+5V
power
supply
3
Output strobe
for
8243
I/O
Expander
4-
1 1
8-bit
quasi-bidirectional port
18-25
8-bit quasi-bidirectional port
26-27
1-2
13
4-bit quasi-bidirectional port
P20-P23
also serve as
a
4-bit
I/O expander bus
for
8243
Input pin testable using the JT1
and JNT1
instructions.
Can
be
designated
the timer/event
counter
input using the
STRT
Designation Pin
#
Function
CNT
instruction.
Also allows
zero-crossover sensing
of
slowly
moving
AC
inputs.
%
RESET
17
Input
used
to
initialize
the proc-
essor by
clearing status
flip-
flops
and
setting
program
counters
to zero.
ALE
12
Address
Latch Enable. Signal
occurring
once every
30
input
clocks,
used as
an output
clock.
XTAL1
15
One
side of crystal or inductor
input for internal oscillator.
Also
input for external source. (Not
TTL
compatible.)
XTAL2
16
Other
side
of
timing control
element.
INSTRUCTION SET
Hexadecimal
Mnemonic
Description Bytes Cycle Opcode
Hexadecimal
ADD
A,R
r
Add
register
to
A
1 1
68-6F
ADD
A,@ R Add
data
memory
to
A
1
1
60-61
ADD
A,#data
Add
immediate
to
A
2 2 03
ADDC
A,R
r
Add
register with carry
1 1
78-7F
ADDC
A,@ R Add
data
memory
with
1
carry
1
70-71
ADDC
A,#dat£
Add
immediate with
2
carry
2 13
ANL
A,R
r
And
register to
A
1 1
58-5F
ANL A,@ R And
data
memory
to
A
1 1
50-51
ANL
A,#data And
immediate
to
A
2
2
53
ORL
A,R
r
Or
register to
A
1
1
48-4F
5
ORL
A,@ R
Or data
memory
to
A
1
1
40-41
5 ORL
A,#data
Or immediate
to
A
2 2 43
I
XRL
A,R
r
Exclusive
Or
register
1
1
D8-DF
3
to
A
<
XRL A,@ R
Exclusive Or
data
1
memory
to
A
1
D0-D1
XRL
A,#data
Exclusive
Or immediate
2
to
A
2
D3
INC
A
Increment
A
1 1
17
DEC A
Decrement A
1
1
07
CLR
A
Clear
A
1 1
27
CPL
A Complement A
1
1
37
DA A
Decimal
adjust
A
1
1
57
SWAP
A Swap
nibbles
of
A
1
1
47
RL A
Rotate
A
left
1 1
E7
RLC A
Rotate
A
left
through
1
carry
1
F7
RR A
Rotate
A
right
1
1
77
RRC
A
Rotate
A
right through
1
carry
1
67
IN A,
P
p
Input port to
A
1
2 08,09,0A
3
OUTL
P
p
A
Output
A
to port
1
2
90,39,3A
•5
MOVD
A,P
p
O
Input
expander
port
1
to
A
2 0C-0F
•3
MOVD
P
p
,A
Output
A
to
expander
1
2
3C-3F
e
port
ANLD P
p
,A
And
A
to
expander
port
1
2
9C-9F
ORLD
P
p
,A Or
A
to
expander
port
1
2 8C-8F
|
INC R
r
Increment
register
1
1
18-1F
o>
INC
@
R
Increment data
memory
1
1
10-11
Mnemonic
Description Bytes
Cycle
Opcode
JMP
addr
Jump
unconditional 2
2
04,24,44,64,
84,A4,C4,E4
JMPP
@
A Jump
indirect
1
2
B3
c
DJNZ
R.addr
o
c
Decrement
register
and
jump on R
not zero
2 2
E8-EF
£ JC
addr
Jump
on carry=
1
2 2
F6
JNC
addr
Jump
on carry=0
2 2
E6
JZ addr Jump
on
A
zero
2 2
C6
JNZ
addr
Jump
on
A
not
zero
2 2
96
JT1 addr
Jump
on T1
=
1
2 2
56
JNT1 addr Jump
on
T1=0
2 2
46
JTF
addr
Jump
on
timer flag 2 2 16
~ CALL
addr
3
O
I RET
Jump
to subroutine
Return
8>
CLRC
£
CPLC
Clear
carry
Complement
carry
MOV
A,R
r
MOV
A,@ R
MOV
A,#data
MOV
R
r
,A
MOV @
R,A
MOV
R
r
,#data
CO
I
MOV@R,#data
10
| SCHA,R
r
XCH
A,@ R
XCHDa,@R
MOVP
A,@ A
Move
register to
A
Move
data
memory
to
A
Move
immediate
to
A
Move A
to register
Move A
to
data
memory
Move
immediate
to
register
Move
immediate
to
data
memory
Exchange A
and
register
Exchange A and
data
memory
Exchange
nibble
of
A
and
register
Move
to
A
from current
page
MOV
A,T
MOV
T,A
STRTT
STRT CNT
STOP TCNT
Read
timer/counter
Load
timer/ counter
Start timer
Start counter
Stop
timer/ counter
2 14,34,54,74
94,B4,D4,F4
2
83
97
A7
F8-FF
F0-F1
23
A8-AF
A0-A1
2
B8-BF
2
BO-B
1
1
28-2F
1
20-21
1
30-31
2
A3
42
62
55
45
65
No
operation
6-35