Intel MCS48 User Manual page 356

8278
Status Description
The
S3-S0
status bits
indicate the
number
of entries
(Oto
8)
in
the
8-level
FIFO.
A
FIFO
overrun
will
lock status
at
1
1 1
1
.
The
overrun condition
will
prevent
further
key
entries
until
cleared.
A
multiple key closure
error
will set
the
KE
flag
and
prevent
further
key
entries
until
cleared.
The
IBF
and
OBF
flags signify the status
of the
8278
data
buffer registers used
to transfer information
(data,
status
or
commands)
to
and from
the
master CPU.
The
IBF
flag
is
set
when
the master
CPU
writes
Data
or
Commands
to
the 8278.
The
I
BF
f
lag
is
cleared by the
8278
during
its
response
to the
Data
or
Command.
The
OBF
flag
is
set
when
the
8278 has output data ready
for the
master
CPU.
This
flag
is
cleared by
a
master
CPU
Data
READ.
The Busy
flag
in
the status
register
is
used
as a
LOCK-
OUT
signal to the
master processor during response
to
any
command
or data write
from
the master.
The
master must
test
the
Busy
flag
before
each
read
(during a sequence)
to
be sure
that
the
8278
is
ready with
valid
DATA.
The
ERROR
and
TONE
outputs from the
8278 are
set
high
for either type
of error.
Both types
of error are cleared
by
the
CLR
input,
by
the
CLEAR ERROR
command,
or
by
a
reset.
The
FIFO and
Display buffers are cleared
independently
of
the
Errors.
FIFO
status
is
used
to indicate the
number
of
characters
in
the
FIFO and
to indicate
whether an
error has occurred.
Overrun occurs
when
the entry
of
another character
into
a
full
FIFO
is
attempted. Underrun occurs
when
the
CPU
tries to
read an
empty
FIFO.
The
character read
will
be
the
last
one
entered.
FIFO
status
will
remain
at
0000 and
the
error condition
will
not be
set.
Data
Read Sequence
Before reading
data,
the master
CPU
must send
a
command
to select
FIFO
or Display
data.
Following the
command,
the
master must
read
STATUS
and
test
the
BUSY
flag
and
the
OBF
flag
to verify that the
8278 has
responded
to the previous
command.
A
typical
DATA
READ
sequence
is
as follows:
J
1_
READ
DISPLAY
OR
FIFO
COMMAND
FROM
MASTER
FIRST
DATA
BYTE
READY
MASTER
NEXT
READS DATA
BYTE
READY
8278
PROCESSING
NEXT BYTE
After the
first
read following a
Read
Display or
Read FIFO
command,
successive reads
may
occur
as
soon
as
OBF
rises.
8278 Data
Write
The
master
CPU
can
write
DATA
to the
8278 Display
buffers by
using the
Ao,
WR
and D0-D7
inputs as follows:
A
,CS INVALID
X
X
\
f
8278 Data Read
The
master
CPU
can
read
DATA
from
the
8278 FIFO
or
Display
buffers
by
using the
Ao,
RD, and D0-D7
inputs as
follows:
A
,
CS
X
X
\
/
The
master
CPU
presents the Data
on
the D0-D7
lines
with
Ao=0 and
then
sends
a
WR
pu
lse.
The
data
is
latched
by
the
8278 on
the
rising
edge
of
WR.
Data
Write
Sequence
Before
writing data to
the 8278, the master
CPU
must
first
send
a
command
to select the desired display entry
mode
and
to specify the address
of
the next data
byte.
Following
the
commands,
the
master
must
read
STATUS
and
test the
BUSY
flag
(B)
and IBF
flag to verify that the
8278 has
responded.
A
typical
sequence
is
shown
below:
<j
—
L__r
The
master sends
a
RD
pulse with
Ao=0 and
CS=0 and
the
8278 responds by outputing data
on
lines
D0-D7.
The data
is
strobed
by
the
trailing
edge
of
RD.
WRITE DISPLAY
8278
MASTER
8278
8278
COMMAND
READY DATA WRITE
READY
READY
FOR
FIRST
BYTE
COMMAND
OR DATA
MASTE
NEXTB
R
WRITES
YTE
8-66
00227A