Intel MCS48 User Manual page 341

8259A
INTERRUPT
MASKS
Each
Interrupt
Request
input
can be
masked
individu-
ally
by the
Interrupt
Mask
Register (IMR)
programmed
through
OCW1.
Each
bit in
the
IMR masks one
interrupt
channel
if it
is
set
(1).
Bit
masks
IRO, Bit
1
masks
IR1
and so
forth.
Masking an
IR
channel does
not affect the
other
channels
operation.
SPECIAL
MASK MODE
Some
applications
may
require
an
interrupt service
routine to
dynamically
alter
the system
priority struc-
ture
during
its
execution under software
control.
For
example,
the routine
may
wish
to inhibit
lower
priority
requests
for
a portion
of
its
execution but enable
some
of
them
for
another
portion.
The
difficulty
here
is
that
if
an
Interrupt
Request
is
acknowledged and
an
End
of Interrupt
command
did not
reset
its
IS
bit
(i.e.,
while executing a service
routine),
the
8259A would have
inhibited
all
lower
priority
requests with no easy
way
for
the routine
to
enable
them
That
is
where
the Special
Mask Mode comes
in. In
the
special
Mask
Mode,
when
a
mask
bit is
set
in
OCW1,
it
inhibits further interrupts
at that
level
and
enables
inter-
rupts from
all
other
levels (lower as well as higher) that
are not
masked.
Thus, any
interrupts
may
be
selectively
enabled by
loading the
mask
register.
The
special
Mask Mode
is
set by
OCW3
where:
SSMM
=
1,
SMM=1,
and
cleared
where
SSMM=1,
SMM
=
0.
BUFFERED
MODE
When
the
8259A
is
used
in
a
large
system where bus
driving buffers are required on
the data bus and
the cas-
cading
mode
is
used, there
exists the
problem
of enabl-
ing buffers.
The
buffered
mode
will
structure the
8259A
to
send an
enable
signal
on
SP/EN
to
enable
the
buffers.
In
this
mode, whenever
the 8259A's data bus
outputs
are ena-
bled,
the
SP/EN
output
becomes
active.
This modification forces the
use
of
software program-
ming
to
determine whether
the
8259A
is
a master
or a
slave.
Bit
3
in
ICW4
programs
the buffered mode, and
bit
2 in
ICW4
determines whether
it
is
a master
or
a
slave.
FULLY
NESTED
MODE
This
mode
is
entered
after initialization
unless another
mode
is
programmed. The
interrupt
requests
are
ordered
in
priority
form through
7
(0
highest).
When
an
interrupt is
acknowledged
the highest priority
request
is
determined and
its
vector
placed on the bus. Additional-
ly,
a
bit
of
the Interrupt Service register (ISO-7)
is set.
This
bit
remains
set
until
the
microprocessor issues an
End
of
Interrupt (EOI)
command
immediately before
returning
from
the service routine, or
if
AEOI
(Automatic
End
of Interrupt)
bit is
set, until
the
trailing
edge
of the
last
INTA.
While
the
IS bit
is
set,
all
further interrupts of
the
same
or lower
priority
are inhibited,
while higher
levels will
generate an
interrupt
(which
will
be
acknowledged
only
if
the
microprocessor
internal
Inter-
rupt
enable
flip-flop
has been
re-enabled through
soft-
ware).
After the
initialization
sequence, IRO
has
the hignest
priority
and IR7 the lowest.
Priorities
can be changed, as
will
be explained,
in
the rotating
priority
mode.
THE
SPECIAL FULLY
NESTED MODE
This
mode
will
be used
in
the
case
of a big
system
where cascading
is
used,
and
the
priority
has
to
be con-
served within
each
slave.
In
this
case the
fully
nested
mode
will
be
programmed
to the
master
(using ICW4).
This
mode
is
similar to the normal nested
mode
with the
following exceptions:
a.
When
an
interrupt
request from a
certain slave
is
in
service
this
slave
is
not
locked out from the master's
priority
logic
and
further interrupt
requests from
higher
priority IR's
within the slave
will
be recognized
by the
master and
will initiate interrupts to
the
proc-
essor.
(In
the
normal nested
mode
a slave
is
masked
out
when
its
request
is in
service
and no
higher
requests from the
same
slave
can be
serviced.)
b.
When
exiting the
Interrupt Service routine the
soft-
ware has
to
check whether
the
interrupt serviced
was
the only one from
that slave. This
is
done
by sending
a non-specific
End
of Interrupt (EOI)
command
to
the
slave
and
then reading
its
In-Service register
and
checking
for zero.
If
it
is
empty, a
non-specific EOI
can be
sent
to
the master
too.
If
not,
no
EOI should be
sent.
8-51