Intel MCS48 User Manual page 98

INSTRUCTION SET
Note:
A
12-bit
address
specification
does
not
cause an
error
if
the
DJNZ
instruction
and
the
jump
target are
on
the
same
page.
If
the
DJNZ
instruction begins
in
location
255
of
a page,
it
must jump
to a target
address on
the following page.
Example:
Increment
values
in
data
memory
locations 50-54.
MOVE
'50'
DEC TO ADDRESS
REG
MOVE
'5'
DEC TO COUNTER
REG
3
INCREMENT CONTENTS OF
LOCATION ADDRESSED BY
REG
INCREMENT ADDRESS
IN
REG
DECREMENT
REG
3
—
JUMP TO
'INCRT
IF
REG
3
NONZERO
'NEXT ROUTINE EXECUTED
IF
R3
IS
ZERO
MOV
R0,#50
MOV
R3,#5
INCRT: INC
@R0
INC R0
DJNZ
R3,
INCRT
NEXT
—
EN
I
Enable
External
Interrupt (Not
in
8021)
000
10
1
External interrupts are enabled.
A
low
signal
on
the
interrupt input pin
initiates
the
interrupt
sequence.
EN
TCNTI
Enable Timer/Counter
Interrupt (Not
in
8021
00 10
10
1
Timer/counter
interrupts
are enabled.
An
overflow
of the timer/counter
initiates
the
interrupt
sequence.
ENT0 CLK
Enable Clock Output
(Not
in
8021
,
8022)
111
10
1
The
test pin
is
enabled
to act as the clock output.
This function
is
disabled
by
a
system
reset.
Example: EMTST0:
ENT0 CLK
;ENABLE
TO
AS
CLOCK OUTPUT
IN
A,Pp
Input Port or Data
to
Accumulator
0000
1
Opp
This
is
a
2-cycle instruction.
Data
present
on
port
'p'
is
transferred
(read) to
the
accumulator.
In
the 8021
IN
A,P2
inputs
P20-P23
to
A0-A3
while
A4-A7
is
set
to zero.
(A)*-
(Pp)
p=1-2
Mnemonics copyright
Intel
Corporation
1976.
4-16