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Intel MultiProcessor Specification

Intel MultiProcessor Specification

Intel multiprocessor specification
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MultiProcessor
Specification
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1.4
May 1997

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Summary of Contents for Intel MultiProcessor

  • Page 1 MultiProcessor Specification Version May 1997...
  • Page 2 Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to implementation of information in this specification. Intel does not warrant or represent that such implementation(s) will not infringe such rights. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark or products.

  • Page 3: Revision History

    Revision Revision History Pre-release Version 1.0. Formerly called “PC+MP Specification” -001 Version 1.1. Resolves conflicts with MCA-based systems. The following changes have been made: 1. Two MP feature information bytes were moved from the BIOS System Configuration Table to the RESERVED area of the MP Floating Pointer Structure.

  • Page 5: Table Of Contents

    Chapter 3 Hardware Specification System Memory Configuration ... 3-1 System Memory Cacheability and Shareability... 3-2 External Cache Subsystem ... 3-4 Locking ... 3-4 Posted Memory Write ... 3-5 Multiprocessor Interrupt Control ... 3-5 3.6.1 APIC Architecture ... 3-5 3.6.2 Interrupt Modes... 3-6 3.6.2.1 3.6.2.2...
  • Page 6 Contents 3.6.6 APIC Identification ... 3-13 3.6.7 APIC Interval Timers... 3-13 3.6.8 Multiple I/O APIC Configurations ... 3-13 RESET Support ... 3-14 3.7.1 System-wide RESET ... 3-14 3.7.2 System-wide INIT... 3-15 3.7.3 Processor-specific INIT... 3-15 System Initial State ... 3-16 Support for Fault-resilient Booting ...
  • Page 7 Appendix A System BIOS Programming Guidelines BIOS Post Initialization ...A-1 Controlling the Application Processors ...A-2 Programming the APIC for Virtual Wire Mode ...A-2 Constructing the MP Configuration Table...A-4 Appendix B Operating System Programming Guidelines Operating System Boot-up ...B-1 Operating System Booting and Self-configuration ...B-2 Interrupt Mode Initialization and Handling ...B-2 Application Processor Startup ...B-3 B.4.1...
  • Page 8 Contents Figures 1-1. Conceptual Overview ... 1-1 1-2. Memory Layout Conventions ... 1-4 2-1. Multiprocessor System Architecture... 2-2 2-2. APIC Configuration ... 2-3 3-1. System Memory Address Map ... 3-2 3-2. PIC Mode ... 3-8 3-3. Virtual Wire Mode via Local APIC ... 3-9 3-4.
  • Page 9 Contents 4-6. Feature Flags from CPUID Instruction ... 4-9 4-7. Bus Entry Fields ... 4-10 4-8. Bus Type String Values... 4-11 4-9. I/O APIC Entry Fields ... 4-12 4-10. I/O Interrupt Entry Fields ... 4-14 4-11. Interrupt Type Values... 4-15 4-12.

  • Page 11: Chapter 1 Introduction

    The MultiProcessor Specification, hereafter known as the “MP specification,” defines an enhancement to the standard to which PC manufacturers design DOS-compatible systems. MP-capable operating systems will be able to run without special customization on multiprocessor systems that comply with this specification. End users who purchase a compliant multiprocessor system will be able to run their choice of operating systems.

  • Page 12: Features Of The Specification

    In no way does the MP specification prevent system manufacturers from adding their own unique value to MP systems. This specification does not define the only way that multiprocessor systems can be implemented. Vendors may, for example, create noncompliant, high-performance, scalable multiprocessor systems that do not have the PC/AT compatibility required by this specification.

  • Page 13: Target Audience

    1.5 Organization of This Document Table 1-1 shows the organization of this document. Table 1-1. Document Organization Chapter Description Overview of the MultiProcessor Specification Specification of the MP hardware Specification of MP configuration information available to OS Specification of default hardware configurations Appendix A...

  • Page 14: Conventions Used In This Document

    Signal names that are followed by the character # represent active low signals. For example, FERR# is active when at its low-voltage state. Throughout this document, the Intel 82489DX APIC is referred to as the “discrete APIC.” The term “integrated APIC” is used to refer to an APIC integrated with other system components, such as the Pentium 735\90 and 815\100 processors.

  • Page 15: Chapter 2 System Overview

    In the realm of multiprocessor architectures, there are several conceptual models for tying together computing elements, and there are a variety of interconnection schemes and details of implementation. Figure 2-1 shows the general structure of a design based on the MP specification.

  • Page 16: Hardware Overview

    2.1 Hardware Overview The MP specification defines a system architecture based on the following hardware components: One or more processors that are Intel architecture instruction set compatible, such as the CPUs in the Intel486 and the Pentium processor family. One or more APICs, such as the Intel 82489DX Advanced Programmable Interrupt Controller or the integrated APIC on the Pentium 735\90 and 815\100 processors.

  • Page 17: Advanced Programmable Interrupt Controller

    I/O unit. The local and I/O units communicate through a bus called the Interrupt Controller Communications (ICC) bus, as shown in Figure 2-2. In a multiprocessor system, multiple local and I/O APIC units operate together as a single entity, communicating with one another over the ICC bus. The APIC units are collectively responsible for delivering interrupts from interrupt sources to interrupt destinations throughout the multiprocessor system.

  • Page 18: System Memory

    Due to the distributed architecture, the APIC local and I/O units can be implemented in either a single chip, such as Intel’s 82489DX interrupt controller, or they can be integrated with other parts of the system’s components. For example, the local APIC may be integrated with the CPU chip, such as Intel’s Pentium processors (735\90, 815\100), and the I/O APIC may be integrated with the...

  • Page 19: Bios Overview

    Initializes the processor and the rest of the system to a known state. Provides run-time device-oriented services. For a multiprocessor system, the BIOS may perform the following additional functions: Pass configuration information to the operating system that identifies all processors and other multiprocessing components of the system.

  • Page 21: Chapter 3 Hardware Specification

    Interval timer usage Support for fault-resilient booting While the bulk of the MP hardware specification pertains to multiprocessor interrupt control, other areas also require some attention. The following sections take up each of these topics in turn. 3.1 System Memory Configuration The MP memory specifications are based on the standard PC/AT memory map, which currently has a physical memory space of four gigabytes, as shown in see Figure 3-1.

  • Page 22: System Memory Cacheability And Shareability

    MultiProcessor Specification FFFF_FFFFH FFFE_0000H FEF0_0000H FEE0_0000H FED0_0000H FEC0_0000H MEMORY-MAPPED 0010_0000H 000F_0000H 000E_0000H 000D_0000H ROM EXTENSIONS 000C_0000H 640K 000A_0000H 0000_0000H PART OF THIS SPECIFICATION UNSHADED ADDRESS REGIONS ARE FOR REFERENCE ONLY AND SHOULD NOT BE CONSTRUED AS THE SOLE DEFINITION OF A PC/AT-COMPATIBLE ADDRESS SPACE.
  • Page 23 Table 3-1. Memory Cacheability Map Addresses (in hex) Size Description 0000_0000h – 640KB Main memory 0009_FFFFh 000A_0000h – 128KB Display buffer for 000B_FFFFh video adapters 000C_0000h – 128KB ROM BIOS for add-on 000D_FFFFh cards 000E_0000h – 128KB System ROM BIOS 000F_FFFFh 0010_0000h –...

  • Page 24: External Cache Subsystem

    MultiProcessor Specification 3.3 External Cache Subsystem Intel-compatible processors support multiprocessing both on the processor bus and on a memory bus, both with and without secondary cache units. Due to the high bandwidth demands of multiprocessor systems, external caches are often employed to improve performance. The existence and implementation details of external caches are not a part of this specification.

  • Page 25: Mp Configuration Table

    MP configuration table described in Chapter 4. The Intel 82489DX APIC is a “discrete APIC” implementation. The programming interface of the 82489DX APIC units serves as the base of the MP specification. Each APIC has a version register that contains the version number of a specific APIC implementation.

  • Page 26: Interrupt Modes

    NOTE: x is a 4-bit hexadecimal number. To encourage future extendibility and innovation, the Intel APIC architecture definition is limited to the programming interface of the APIC units. The ICC bus protocol and electrical specifications are considered implementation-specific. That is, while different versions of APIC implementations may execute the same binary software, different versions of APIC components may be implemented with different bus protocols or electrical specifications.

  • Page 27: Pic Mode

    Virtual Wire Mode. An MP operating system is booted under either one of the two PC/AT- compatible modes. Later the operating system switches to Symmetric I/O Mode as it enters multiprocessor mode. The interrupt modes are implemented by a combination of hardware and software. The hardware and programming specifications for each of these modes are further defined in the following subsections.

  • Page 28: Pic Mode

    MultiProcessor Specification IMCR REG. MARK LINTIN0 LINTIN1 LINTIN0 RESET ICC BUS INTERRUPT INPUTS SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH. The IMCR is supported by two read/writable or write-only I/O ports, 22h and 23h, which receive address and data respectively. To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR.

  • Page 29: Virtual Wire Mode

    3.6.2.2 Virtual Wire Mode Virtual Wire Mode provides a uniprocessor hardware environment capable of booting and running all DOS shrink-wrapped software. In Virtual Wire Mode, as shown in Figure 3-3, the 8259A-equivalent PIC fields all interrupts, and the local APIC of the BSP becomes a virtual wire, which delivers interrupts from the PIC to the BSP via the local APIC’s local interrupt 0 (LINTIN0).

  • Page 30: Virtual Wire Mode Via I/O Apic

    MultiProcessor Specification Figure 3-3 shows how Virtual Wire Mode can be implemented through the BSP’s local APIC. It is also permissible to program the I/O APIC for Virtual Wire Mode, as shown in Figure 3-4. In this case the interrupt signal passes through both the I/O APIC and the BSP’s local APIC.

  • Page 31: Default Configurations

    3.6.2.3 Symmetric I/O Mode Some MP operating systems operate in Symmetric I/O Mode. This mode requires at least one I/O APIC to operate. In this mode, I/O interrupts are generated by the I/O APIC. All 8259 interrupt lines are either masked or work together with the I/O APIC in a mixed mode. See Figure 3-5 for an overview of Symmetric I/O Mode.

  • Page 32: Assignment Of System Interrupts To The Apic Local Unit

    MultiProcessor Specification 3.6.3 Assignment of System Interrupts to the APIC Local Unit The APIC local unit has two general-purpose interrupt inputs, which are reserved for system interrupts. These interrupt inputs can be individually programmed to different operating modes. Like the I/O APIC interrupt lines, the local APIC interrupt line assignments of a non-PC/AT- compatible system are system implementation specific.

  • Page 33: Apic Identification

    3.6.6 APIC Identification Systems developers must assign APIC local unit IDs and ensure that all are unique. There are two acceptable ways to assign local APIC IDs, as follows: By hardware. The ID of each APIC local unit is sampled from the appropriate pins at RESET. By the BIOS.

  • Page 34: Reset Support

    MultiProcessor Specification REG. MARK INTR/LINT0 ICC BUS Figure 3-6. Multiple I/O APIC Configurations 3.7 RESET Support To bring all circuitry in a computer system to an initial state, computer systems require a system- wide reset capability. To support multiple processors, a compliant system requires a processor- specific reset or initialization capability in addition to the typical system-wide reset and initialization capabilities.

  • Page 35: System-Wide Init

    3.7.3 Processor-specific INIT A processor-specific INIT is one of the basic multiprocessor support functions of a compliant multiprocessor system, along with processor startup and shutdown. With it, the BSP can selectively initialize an AP for subsequent startup or recover an AP from a fatal system error. This type of INIT function is exclusively used by the MP operating system or BIOS self-test routine.

  • Page 36: System Initial State

    MultiProcessor Specification 3.8 System Initial State The system initial state is the state before the BIOS gives control to the operating system. It is identical to the system initial state of a typical PC/AT system, with the additional MP components in the following state: 1.

  • Page 37: Chapter 4 Mp Configuration Table

    The operating system must have access to some information about the multiprocessor configuration. The MP specification provides two methods for passing this information to the operating system: a minimal method for configurations that conform to one of a set of common hardware defaults, and a maximal method that provides the utmost flexibility in hardware design.
  • Page 38 MultiProcessor Specification The following two data structures are used: 1. The MP Floating Pointer Structure. This structure contains a physical address pointer to the MP configuration table and other MP feature information bytes. When present, this structure indicates that the system conforms to the MP specification. This structure must be stored in at...

  • Page 39: Mp Floating Pointer Structure

    MP Floating Pointer Structure An MP-compliant system must implement the MP floating pointer structure, which is a variable length data structure in multiples of 16 bytes. Currently, only one 16-byte data structure is defined. It must span a minimum of 16 contiguous bytes, beginning on a 16-byte boundary, and it must be located within the physical address as specified in the previous section.
  • Page 40 MultiProcessor Specification Table 4-1. MP Floating Pointer Structure Fields (continued) Offset Field (in bytes:bits) MP FEATURE INFORMATION BYTE 1 MP FEATURE 12:0 INFORMATION BYTE 2 12:7 MP FEATURE INFORMATION BYTES 3-5 The MP feature information byte 1 specifies the MP system default configuration type. If nonzero, the system configuration conforms to one of the default configurations.

  • Page 41: Mp Configuration Table Header

    MP Configuration Table Header Figure 4-3 shows the format of the header of the MP configuration table, and Table 4-2 explains each of the fields. RESERVED ENTRY COUNT space space space space CHECKSUM P (50h) Figure 4-3. MP Configuration Table Header Version 1.4 EXTENDED TABLE...

  • Page 42: Base Mp Configuration Table Entries

    MultiProcessor Specification Table 4-2. MP Configuration Table Header Fields Offset Field (in bytes) SIGNATURE BASE TABLE LENGTH SPEC_REV CHECKSUM OEM ID PRODUCT ID OEM TABLE POINTER OEM TABLE SIZE ENTRY COUNT ADDRESS OF LOCAL APIC EXTENDED TABLE LENGTH EXTENDED TABLE...

  • Page 43: Processor Entries

    Table 4-3. Base MP Configuration Entry Description Processor I/O APIC I/O Interrupt Assignment Local Interrupt Assignment * All other type codes are reserved. 4.3.1 Processor Entries Figure 4-4 shows the format of each processor entry, and Table 4-4 defines the fields. CPU FLAGS RESERVED In systems that use the MP configuration table, the only restriction placed on the assignment of...

  • Page 44: Processor Entry Fields

    CPUID instruction, the BIOS must fill these and future reserved fields with information returned by the processor in the EDX register after a processor reset. See the Pentium Processor User’s Manual and Intel Processor Identification with the CPUID Instruction (AP-485) for details on the CPUID instruction.

  • Page 45: Intel486™ And Pentium ® Processor Signatures

    Values not shown are reserved for future processors. Refer to the documentation of each new processor for its family and model values. 1111 1111 1111 a Intel releases information about stepping numbers as needed. Table 4-6. Feature Flags from CPUID Instruction Name Description On-chip Floating Point Unit 1–6...

  • Page 46: Bus Entries

    MultiProcessor Specification 4.3.2 Bus Entries Bus entries identify the kinds of buses in the system. Because there may be more than one bus in a system, each bus is assigned a unique bus ID number by the BIOS. The bus ID number is used by the operating system to associate interrupt lines with specific buses.
  • Page 47 Table 4-8. Bus Type String Values Bus Type String CBUS CBUSII EISA FUTURE INTERN MBII MPSA NUBUS PCMCIA XPRESS Each bus in a system must have a unique BUS ID if any one of the following criteria are true: The bus does not share its memory address space with another bus. The bus does not share its I/O address space with another bus.

  • Page 48: I/O Apic Entries

    MultiProcessor Specification 4.3.3 I/O APIC Entries The configuration table contains one or more entries for I/O APICs. Figure 4-6 shows the format of each I/O APIC entry, and Table 4-9 explains each field. I/O APIC FLAGS RESERVED Table 4-9. I/O APIC Entry Fields...

  • Page 49: I/O Interrupt Entry

    2. No Interrupt Assignment Entries are declared for any of the bus source interrupts, and the operating system uses some other bus-specific knowledge of bus interrupt schemes in order to support the bus. This operating system bus-specific knowledge is beyond the scope of this specification.

  • Page 50: I/O Interrupt Entry Fields

    MultiProcessor Specification Table 4-10. I/O Interrupt Entry Fields Field ENTRY TYPE INTERRUPT TYPE SOURCE BUS ID SOURCE BUS IRQ DESTINATION I/O APIC ID DESTINATION I/O APIC INTIN# 4-14 Offset Length (in bytes:bits) (in bits) Description Entry type 3 identifies an I/O interrupt entry.

  • Page 51: Local Interrupt Assignment Entries

    Table 4-11. Interrupt Type Values Interrupt Type* Description ExtINT * All other values are reserved. 4.3.5 Local Interrupt Assignment Entries These configuration table entries tell what interrupt source is connected to each local interrupt input of each local APIC. Figure 4-8 shows the format of each entry, and Table 4-12 explains each field.

  • Page 52: Local Interrupt Entry Fields

    MultiProcessor Specification Table 4-12. Local Interrupt Entry Fields Field ENTRY TYPE INTERRUPT TYPE SOURCE BUS ID SOURCE BUS IRQ DESTINATION LOCAL APIC ID DESTINATION LOCAL APIC LINTIN# 4-16 Offset (in Length bytes:bits) (in bits) Description Entry type 4 identifies a local interrupt entry.

  • Page 53: Extended Mp Configuration Table Entries

    Extended MP Configuration Table Entries A variable number of variable-length entries are located in memory, immediately following entries in the base section of the MP configuration table described in Section 4.3. These entries compose the extended section of the MP configuration table. Each entry in the extended section of the table has three elements: ENTRY TYPE ENTRY LENGTH...

  • Page 54: System Address Space Mapping Entries

    MultiProcessor Specification 4.4.1 System Address Space Mapping Entries System Address Space Mapping entries define the system addresses that are visible on a particular bus. Each bus defined in the Base Table can have any number of System Address Space Mapping entries included in the Extended Table.

  • Page 55: System Address Space Mapping Entry Fields

    Table 4-14. System Address Space Mapping Entry Fields Offset Field bytes:bits) ENTRY TYPE ENTRY LENGTH BUS ID ADDRESS TYPE ADDRESS BASE LENGTH If any main memory address is mapped to a software visible bus, such as PCI, it must be explicitly declared using a System Address Space Mapping entry.
  • Page 56 MultiProcessor Specification Figure 4-10. Example System with Multiple Bus Types and Bridge Types Since all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices (i.e., ISA, EISA) should support all possible addresses to that bus.

  • Page 57: Bus Hierarchy Descriptor Entries

    4.4.2 Bus Hierarchy Descriptor Entry If present, Bus Hierarchy Descriptor entries define how I/O buses are connected relative to each other in a system with more than one I/O bus. Bus Hierarchy Descriptors are used to supplement System Address Mapping entries to describe how addresses propagate to particular buses in systems where address decoding cannot be completely described by System Address Space Mapping entries alone.

  • Page 58: Compatibility Bus Address Space Modifier Entries

    MultiProcessor Specification Table 4-15 Bus Hierarchy Descriptor Entry Fields Offset Field (in bytes:bits) ENTRY TYPE ENTRY LENGTH BUS ID BUS INFORMATION:SD PARENT BUS For buses where the BUS INFORMATION:SD bit is set, System Address Mappings may not be needed. Since the bus is defined as being subtractive decode, the range of addresses that appear on the bus can be derived from address decoding information for parent and peer buses.

  • Page 59: Compatibility Bus Address Space Modifier Entry

    For example, a host bus bridge for a PCI bus that provides ISA compatibility may decode a predefined range of addresses used for ISA device support in addition to the addresses used for PCI devices on that bus. A Compatibility Bus Address Space Modifier can be used in this case to add these predefined address ranges to the list specified by System Address Space Mapping entries for that PCI bus.

  • Page 60: Compatibility Bus Address Space Modifier Entry Fields

    MultiProcessor Specification Table 4-16. Compatibility Bus Address Space Modifier Entry Fields Offset Field bytes:bits) ENTRY TYPE ENTRY LENGTH BUS ID ADDRESS MODIFIER:PR PREDEFINED RANGE LIST 4 PREDEFINED RANGE LIST may take one of the values from Table 4-17. The value of PREDEFINED RANGE LIST indicates the set of address ranges that are to be either added to or subtracted from the address range associated with the BUS ID.

  • Page 61: Chapter 5 Default Configurations

    The default system configurations include configurations that use the discrete APIC, such as the Intel 82489DX or its equivalent, and configurations that use the integrated APIC, such as the Pentium processors (735\90, 815\100). Each default configuration has a unique code. Table 5-1 specifies the configuration associated with each code.

  • Page 62: Default Configurations

    MultiProcessor Specification Table 5-1. Default Configurations Default Number Config Code of CPUs Type EISA EISA ISA + PCI EISA + PCI MCA + PCI 8-255 Reserved for MP future use. The default system configurations are designed to support dual-processor systems with fixed configurations.

  • Page 63: Default Configuration For Discrete Apic

    INTEL486 CPU 1 IMCR INTR PNMI PINT LOCAL 82489DX APIC REG. MARK LINTIN0 INTR RESET ICC BUS I/O BUS IRQ1 8254 TIMER IRQ8# IRQ13 EISA DMA CHAINING FROM BSP FERR# FERR IGNNE# SAMPLING ABFULL ABFULL (PS/2 MOUSE) SAMPLING EDGE/LEVEL TRIGGER POLARITY CONTROL IRQ3-7, 9-12,14,15...

  • Page 64: Integrated Apic Configurations

    MultiProcessor Specification The INTA TRAP and GLUE in the figure are the additional hardware interface logic needed for the 82489DX APIC. INTA TRAP conditions all interrupt acknowledge cycles with ExtINTA to steer the vector either from the 8259A PIC or the APIC. INTA TRAP is also responsible for preventing the interrupt acknowledge cycle from reaching the 8259A PIC, in case ExtINTA is negated when PINT is activated.

  • Page 65: Default Configuration For Integrated Apic

    PENTIIUM (735\90, 815\100) CPU1 LOCAL APICEN APIC REG. MARK INIT SMI# ICC BUS IRQ1 8254 TIMER IRQ8# INT8 IRQ13 EISA DMA CHAINING FROM BSP FERR# FERR IGNNE# SAMPLING ABFULL ABFULL (PS/2 MOUSE) SAMPLING PIRQ0-3 EDGE/LEVEL TRIGGER POLARITY CONTROL IRQ3-7, IRQx 9-12,14,15 PIRQ LITMx...

  • Page 66: Assignment Of I/O Interrupts To The Apic I/O Unit

    The interconnection of I/O APIC interrupt lines is the same as for the 82489DX APIC configuration. However, for PCI system implementations based on the Intel PCI chipset, the PCI PIRQx lines are mapped to the ISA IRQx via a mapping register. This type of implementation makes PCI interrupt lines appear as ISA interrupt lines, which are transparent to the operating system.

  • Page 67: Eisa And Irq13

    Certain EISA chipsets do not bring out the IRQ0, 8254 timer interrupt, and IRQ13 EISA DMA chaining interrupt signals. If these signals are not directly available, INTIN2 and INTIN13 should be disabled. Refer to Section 5.3.1 for more details. 5.3.1 EISA and IRQ13 IRQ13 is a shared interrupt as defined in the EISA bus specification.
  • Page 68 MultiProcessor Specification The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software.

  • Page 69: Appendix A System Bios Programming Guidelines

    Depending on the MP components in a multiprocessor system, the system BIOS may have the following additional responsibilities: 1. Put the APs to sleep, so that they do not all try to execute the same BIOS code as the BSP.

  • Page 70: Controlling The Application Processors

    MultiProcessor Specification A.2 Controlling the Application Processors Provision must be made to prevent all processors from executing the BIOS after a power-on RESET. System developers may choose to do this by the hardware alone or by cooperation between hardware and the BIOS. In the latter case, the BIOS may be used for selecting the BSP and placing all APs to sleep after POST.

  • Page 71: A-1. Programming Local Apic For Virtual Wire Mode

    ;-----------------------------------------------------------------------; ; InitLocalAPIC( ) ;-----------------------------------------------------------------------; Initialize the local APIC to virtual wire mode. ;-----------------------------------------------------------------------; 0FEE000F0H LVT1 0FEE00350H LVT2 0FEE00360H APIC_ENABLED 000000100H public InitLocalAPIC InitLocalAPIC proc near push push push al,080h 070h,al al,021h push al,0ffh 021h,al al,0a1h push al,0ffh 0a1h,al extrn pmode_on : near call pmode_on...

  • Page 72: Constructing The Mp Configuration Table

    MultiProcessor Specification esi,LVT1 eax,[esi] eax,0FFFE00FFH eax,000005700H [esi],eax ; Program LVT2 as NMI, which delivers the signal on the NMI signal of all ; processors' cores listed in the destination. esi,LVT2 eax,[esi] eax,0FFFE00FFH eax,000005400H [esi],eax extrn pmode_off : near call pmode_off...
  • Page 73 The BSP is responsible for positioning the MP configuration table. The table can be located within any unreported, hidden system memory space or within the BIOS ROM region. The BIOS can select any unused space in those regions. For example, some PC/AT systems implement the Extended BIOS Data Segment, a 1-Kbyte block usually positioned at the top of the PC’s 640K base memory.

  • Page 75: Appendix B Operating System Programming Guidelines

    The goal of the MP specification is to transfer enough information about the hardware environment to the operating system that a single, shrink-wrapped, operating-system binary can boot-up and fully utilize a wide variety of multiprocessor systems. The following sections explain how the operating system can take advantage of this specification to handle these operations: 1.

  • Page 76: Operating System Booting And Self-Configuration

    (IMCR) has a value of zero. The operating system should not try to read the IMCR because it may not exist. The operating system should switch over to Symmetric I/O Mode to start multiprocessor operation. If the IMCRP bit of the MP feature information bytes is set, the operating system must set the IMCR to APIC mode.

  • Page 77: Application Processor Startup

    Then the operating system should enable its own local APIC, thereby allowing IPI communications with other APIC-based processors. At this time, the APs’ local APICs have interrupts disabled. Interrupts must remain disabled at the APs’ local APICs while the BSP is enabling the I/O APIC and bringing the system to the normal operating state.

  • Page 78: Using Init Ipi

    Optionally, the operating system can make use of the information provided by the integrated APIC error register. Integrated local APIC units on Intel Architecture processors provide an APIC error register that indicates the reason for non-delivery of an APIC message. Reasons for non-delivery include SEND_ACCEPT and RECEIVE_ACCEPT errors that are generated when no processor responds to a message on the APIC bus.

  • Page 79: B.5 Ap Shutdown Handling

    The operating system must not rely on any code being executed after the delivery Version 1.4 Operating System Programming Guidelines Intel processors with local APIC versions of state immediately after RESET or INIT, a STARTUP IPI causes it The effect is to set CS:IP to VV00:0000h.

  • Page 80: Other Ipi Applications

    MultiProcessor Specification of an INIT IPI used to shut down an AP. As a result, the operating system must ensure that any required state information is captured and that caches are flushed as necessary before sending the INIT IPI. In order to do a complete system shutdown, followed by a warm restart if necessary, the operating system should return the system to a state similar to that at power-on.

  • Page 81: Supporting Unequal Processors

    Operating System Programming Guidelines interrupt. The distributed APIC architecture, by its nature, is more vulnerable to spurious interrupt, because the device interrupt may be latched and recognized without the INTA cycle. To ensure that spurious interrupts are handled properly, it is strongly recommended that the device drivers must read the status register before servicing the device.

  • Page 83: Appendix C System Compliance Checklist

    Are all locked operations visible to all processors? Are locked operations guaranteed on aligned memory operations? Are memory writes observed externally in same order as programmed? 3. Multiprocessor Interrupt Control Does each processor have its own local APIC? Is there a processor designated for booting?

  • Page 85: Appendix D Multiple I/O Apic Multiple Pci Bus Systems

    The information in this specification describes the majority of multiprocessor systems. This appendix provides clarifications for implementors who are considering designs with more than one I/O APIC. In particular, a number of proposed systems will incorporate multiple I/O APICs in order to support multiple PCI buses.

  • Page 86: Fixed Interrupt Routing

    MultiProcessor Specification If IMCR is implemented but the system includes one or more I/O APICs that are not controlled through IMCR, the hardware must accomplish routing changes for such I/O APICs by some other means when the system switches into symmetric I/O mode. These routing changes must be done without requiring any additional intervention from software.

  • Page 87: Bus Entries In Systems With More Than One Pci Bus

    Fixed interrupt routing also implies a restriction on software that is implicit but important in the context of systems with more than one I/O APIC. The operating system must program I/O APICs to handle only the interrupts for which the MP configuration table contains corresponding I/O interrupt assignment entries.

  • Page 89: Appendix E Errata

    The following sections provided here are intended to replace the corresponding sections in the main body of the specification. The sections provided here are shown in their entirety to provide context for the changes. Changes contained below are marked with double underlined text which shows changes relative to the version of the sections that are provided in the main body of the specification.

  • Page 90: Mp Floating Pointer Structure Fields

    MultiProcessor Specification Table 4-1. MP Floating Pointer Structure Fields Offset Field (in bytes:bits) SIGNATURE PHYSICAL ADDRESS POINTER LENGTH SPEC_REV CHECKSUM MP FEATURE INFORMATION BYTE 1 MP FEATURE 12:0 INFORMATION BYTE 2 12:6 12:7 MP FEATURE INFORMATION BYTES 3-5 The MP feature information byte 1 specifies the MP system default configuration type. If nonzero, the system configuration conforms to one of the default configurations.
  • Page 91 information byte 2, the IMCR present bit, is used by the operating system to determine whether PIC Mode or Virtual Wire Mode is implemented by the system. The physical address pointer field contains the address of the beginning of the MP configuration table.
  • Page 92 MultiProcessor Specification Table 4-14. System Address Space Mapping Entry Fields Offset Field (in bytes:bits) ENTRY TYPE ENTRY LENGTH BUS ID ADDRESS TYPE ADDRESS BASE LENGTH If any main memory address is mapped to a software visible bus, such as PCI, it must be explicitly declared using a System Address Space Mapping entry.
  • Page 93 Since all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices (i.e., ISA, EISA) should support all possible addresses to that bus. In general, the MP configuration table must provide entries to describe system address space mappings for all I/O buses present in the system.

  • Page 94: Bus Hierarchy Descriptor Entry

    MultiProcessor Specification BUS INFO RESERVED Figure 4-11. Bus Hierarchy Descriptor Entry Table 4-15 Bus Hierarchy Descriptor Entry Fields Offset Field (in bytes:bits) ENTRY TYPE ENTRY LENGTH BUS ID BUS INFORMATION:SD PARENT BUS For buses where the BUS INFORMATION:SD bit is set, System Address Mappings may not be needed.

  • Page 95: Glossary

    Invalidate: Change the state of a cache line to the Invalid state. IPI: Interprocessor interrupt. MESI: A cache coherency protocol named after the states that cache lines may have: Modified, Exclusive, Shared, Invalid. MP: A multiprocessor system is one with two or more processors. PIC: Programmable Interrupt Controller. Version 1.4 Glossary-1...
  • Page 96 Symmetric I/O Mode: One of three interrupt modes defined by the MP specification. In this mode, the APICs are fully functional, and interrupts are generated and delivered to the processors by the APICs. Any interrupt can be delivered to any processor. This is the only multiprocessor interrupt mode.
  • Page 97 Order Number: 242016-006 Printed in U.S.A.

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