Intel MCS48 User Manual page 294

8251
A
Synchronous
Mode
(Transmission)
The
TxD
output
is
continuously high
until
the
CPU
sends
its
first
character to the
8251A
which
usually
is
a
SYNC
character.
When
the
CTS
line
goes low, the
first
character
is
serially transmitt ed ou
t.
All characters are shifted
out on
the falling
edge of TxC.
Data
is
shifted
out
at
the
same
rate as
the
TxC.
Once
transmission has
starte d,
the data stream
at the
TxD
output
must
continue
at
the
TxC
rate.
If
the
CPU
does not
provide the 8251
A
with
a
data character before the
8251
A
Transmitter
Buffers
become
empty,
the
SYNC
characters
(or
character
if
in single
SYNC
character
mode)
will
be
automatically
inserted
in
the
TxD
data stream. In this case,
the
TxEMPTY
pin
is
raised high to
signal
that the
8251A
is
empty
and
SYNC
characters are being sent out.
TxEMPTY
does not go low
when
the
SYNC
is
being
shifted
out
(see
figure
below).
The
TxEMPTY
pin
is
internally reset
by
a
data character being written
into the
8251
A.
AUTOMATICALLY
1
NSERTED BY USART
\
TxD
DATA DATA SYNC1 SYNC
2
DATA
/
wwww
NOMINAL CENTER OF
LAST BIT
Synchronous
Mode
(Receive)
In this
mode, character synchronization can be
internally
or externally achieved.
If
the
SYNC
mode
has been pro-
grammed,
ENTER HUNT
command
should be included
in
the
first
command
instruction
word
written.
Da
ta
o
n the
RxD
pin
is
then
sampled
in
on
the
rising
edge of
RxC.
The
content of the
Rx
buffer
is
compared
at
every
bit
boundary
with the
first
SYNC
character until a
match
occurs.
If
the
8251
A
has been
programmed
for
two
SYNC
characters,
the
subsequent
received character
is
also
compared;
when
both
SYNC
characters have been
detected, the
USART
ends the
HUNT
mode
and
is
in
character synchronization.
The
SYNDET
pin
is
then
set high,
and
is
reset
automatically by
a
STATUS
READ.
If
parity
is
programmed,
SYNDET
will
not be
set until the
middle
of the parity
bit
instead
of
the
middle
of the
last
data
bit.
In
the external
SYNC
mode,
synchronization
is
achieved by
applying
a
high
level
on
the
SYNDET
pin,
thus forcing the
8251
A
out of
th e
HU NT
mode. The
high
level
can be
removed
after
one
RxC
cycle.
An
ENTER
HUNT
command
has
no
effect
in
the asynchronous
mode
of operation.
Parity error
and
overrun
error are
both checked
in
the
same
way
as in
the Asynchronous
Rx
mode.
Parity
is
checked
when
not
in
Hunt,
regardless
of whether the Receiver
is
enabled
or not.
The
CPU
can
command
the receiver to enter the
HUNT
mode
if
synchronization
is
lost.
This
will
also set
all
the
used character
bits in
the buffer to
a
"one",
thus prevent-
ing a possible false
SYNDET
caused
by data that
happens
to
be
in
the
Rx
Buffer
at
ENTER
HUNT
time.
Note
that
the
SYNDET
F/F
is
reset at
each Status Read,
regardless
of
whether
internal or external
SYNC
has
been programmed.
This
does not
cause the
8251A
to return to the
HUNT
mode.
When
in
SYNC
mode,
but not
in
HUNT,
Sync
Detec-
tion
is
still
functional,
but only occurs
at
the
"known"
word
boundaries.
Thus,
if
one
Status
Read
indicates
SYN-
DET
and
a
second
Status
Read
also indicates
SYNDET,
then the programmed
SYNDET
characters
have been
re-
ceived since the previous Status Read.
(If
double
character
sync has been
programmed,
then both sync
characters
have
been contiguously received to gate
a
SYNDET
indication.)
When
external
SYNDET
mode
is
selected, internal
Sync
Detect
is
disabled,
and
the
SYNDET
F/F
may
be set at
any
bit
boundary.
CHARACTER LENGTH
1 1
1 1
5
BITS
6
BITS
7
BITS
8
BITS
PARITY ENABLE
(1
= ENABLEI
(0= DISABLE)
EVEN
PARITY
GENERATION/CHECK
1
=
EVEN
0»ODD
EXTERNAL SYNC DETECT
1
=
SYNDET
IS
AN
INPUT
=
SYNDET
IS
AN OUTPUT
SINGLE CHARACTER SYNC
1
=
SINGLE SYNC CHARACTER
=
DOUBLE SYNC CHARACTER
NOTE:
IN
EXTERNAL SYNC MODE,
PROGRAMMING DOUBLE CHARACTER
SYNC WILL AFFECT ONLY THE
Tx.
Figure
8.
Mode
Instruction
Format,
Synchronous
Mode
CPU BYTES
(5-8
BITS/CHAR)
DATA CHARACTERS
ASSEMBLED
SERIAL
DATA OUTPUT
(TxD)
SYNC
CHAR
1
SYNC
CHAR
2
DATA CHARACTERS
RECEIVE
FORMAT
SERIAL
DATA
INPUT
(RxD)
SYNC
CHAR
1
SYNC
CHAR
2
DATA CHARACTERS
CPU BYTES
(5-8
BITS/CHAR)
DATA CHARACTERS
Figure
9.
Data Format,
Synchronous
Mode
8-4 0021
6A