Intel MCS48 User Manual page 242

2101A
FAMILY
2101A
(350 ns
ACCESS
TIME)
A.C.
CHARACTERISTICS
READ CYCLE
T
A
= 0°C
to
70°C,
V
cc
=
5V
±5%,
unless
otherwise
specified.
Symbol
Parameter Min.
T
t11
Typ. Max.
Unit Test Conditions
tRC
Read
Cycle
350
ns
tA
Access
Time 350
ns
t
r ,
t
f
= 20ns
tco
Chip Enable
To
Output
240
ns
Input
Levels
=
0.8V
or 2.0V
tfDD
Output
Disable
To
Output 180
ns
Timing Reference
= 1.5V
t
DF
[2]
Data
Output
to
High
Z
State
150 ns
Load
=
1
TTL
Gate
tQH
Previous
Read
Data Valid
after
change
of
Address
40
ns
and
C
L
- 100pF.
WRITE CYCLE
Symbol
Parameter Min.
Typ. Max.
Unit Test Conditions
twc
Write Cycle 220
ns
*AW
Write Delay 20
ns
t
r
,
t
f
= 20ns
tew
Chip Enable
To
Write 200 ns
Input Levels
= 0.8V
or
2.0V
t
DW
Data Setup 200
ns
Timing Reference
=
1.5V
tDH
Data Hold
ns
Load
=
1
TTL
Gate
t
WP Write
Pulse
200
ns
andC
L
= 100pF.
%R
Write Recovery
ns
^S Output
Disable Setup
20
ns
2101A-4 (450 ns
ACCESS
TIME)
A.C.
CHARACTERISTICS
READ CYCLE
T A
= 0°C
to
70°C,
V
cc
=
5V
±5%,
unless otr erwise specified.
Symbol
Parameter
Min. Typ.
Max.
Unit Test Conditions
tRC
Read Cycle
450
ns
tA
Access
Time 450
ns t
r
,
t
f
= 20ns
tco
Chip Enable
To
Output
310
ns
Input
Levels
=
0.8V
or
2.0V
l
OD
Output
Disable
To
Output 250 ns
Timing Reference
=
1.5V
t
DF
I2J
Data Output
to
High
Z
State
200
ns
Load
=
1
TTL
Gate
tQH
Previous
Read Data
Valid
after
change
of
Address
40
ns
and
C
L
= 100pF.
WRITE CYCLE
Symbol
Parameter Min.
T
[11
Typ. Max. Unit Test Conditions
l
WC Write Cycle
270
ns
tAW
Write Delay
20 ns
t
r
,
t
f
=
20ns
tew
Chip Enable
To
Write
250 ns
Input Levels
=
0.8V
or
2.0V
tDW
Data Setup 250
ns
Timing Reference
=
1.5V
tDH
Data Hold
ns
Load
=
1
TTL
Gate
t
WP Write Pulse 250
ns
and
C
L
= 100pF.
tWR Write Recovery ns
t
DS
Output
Disable
Setup
20
ns
NOTES:
1
.
Typical values are for
T
A
= 25°
C and nomina[
supply
voltage.
2.
tQF
is
with respect to the
trailing
edge of
CEi
,
CE2,
or
OD,
whichever occurs
first.
7-4