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iny
2716
16K
(2K x
8)
UV ERASABLE
PROM
Fast
Access Time
—
350 ns Max.
2716-1
—
390 ns Max.
2716-2
—
450 ns Max. 2716
Single
+
5V Power
Supply
Low
Power
Dissipation
—
525
mW
Max.
Active
Power
—
132
mW
Max. Standby
Power
Pin
Compatible
to
Intel®
5V
ROMs
(231
6E,
2332A,
and
2364A)
and 2732
EPROM
Simple
Programming Requirements
Single Location
Programming
Programs
with
One
50
ms
Pulse
Inputs
and Outputs TTL Compatible
during
Read and Program
Completely
Static
The
Intel
5
'
2716
is
a
16,384-bit
ultraviolet
erasable
and
electrically
programmable
read-only
memory
(EPROM). The 2716
operates
from
a
single 5-volt
power
supply, has
a static
standby
mode, and
features
fast
single
address location
program-
ming.
It
makes
designing with
EPROMs
faster,
easier
and
more
economical. For production
quantities,
the
2716
user
can
convert
rapidly to
Intel's
pin-for-pin
compatible
16K
ROM
(the
2316E)
or the
new
32K
and
64K
ROMs
(the
2332A
and
2364A
respectively).
The
2716, with
its
single 5-volt
supply
and
with an
access
time
up
to
350
ns,
is
ideal for
use
with
the
newer
high
performance
+5V
microprocessors such
as
Intel's
8085
and 8086.
The 2716
is
also
the
first
EPROM
with
a static
standby
mode
which
reduces
the
power
dissipation
without
increasing access time.
The
maximum
active
power
dissipation
is
525
mW
while the
maximum
standby
power
dissipation
is
only
132
mW,
a
75%
savings.
The 2716
has the simplest
and
fastest
method
yet devised
for
programming
EPROMs
—
single
pulse
TTL
level
programming.
No
need
for
high voltage pulsing
because
all
programming
controls
are
handled by
TTL
signals.
Program any
location
at
any
time—
either individually, sequentially or at
random,
with
the
271
6's
single
address location
programming.
Total
programming
time
for
all
1
6,384
bits
is
only
1
00
seconds.
PIN
CONFIGURATION
2716
2732'
tRefer
to
2732
data sheet
for
specifications
PIN
NAMES
A0-
A
10
ADDRESSES
CE/PGM
CHIP
ENABLE/PROGRAM
OE
OUTPUT ENABLE
°0-°;
OUTPUTS
MODE
SELECTION
\-.
PINS
MODE
^-.
CE/PGM
(18)
OE
(201
Vpp
121)
v
cc
(24)
OUTPUTS
(9-11,
13-17)
Read
V|L
VlL
+5
+5
D
OUT
Standby
V|H
Don't Care
+6
+5
High
Z
Program
Pulsed V| L
to
V|H
V|H
+25
+5
D|N
Program
Verity
VlL
VlL
+25
+5
DouT
Program
Inhibit
VlL
V|H
+25
+5
High
Z
BLOCK DIAGRAM
OUTPUT ENABLE
CHIP
ENABLE
AND
PROG
LOGIC
AO -Alb
ADDRESS
INPUTS
OUTPUT BUFFERS
INTEL
CORPORATION ASSUMES
NO RESP0NSBUTY
FOR
THE USE
OF ANY
CRCUTRY
OTHER THAN CRCUITRY EMBODIED
IN
AN
INTEL
PRODUCT.
NO
OTHER
CIRCUIT
PATENT
LICENSES ARE
IMPLIED.
e
INTEL
CORPORATION, 1979
7-16
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