Intel MCS48 User Manual page 381

8291
When
the 8291
is
addressed
to
talk,
it
uses the data-out
register to
move
data
onto
the
GPIB.
Upon
a write
to this
register,
the 8291
initiates
and completes
the
handshake
while
sending the byte out over the bus.
When
the
RFD/DAV
holdoff
mode
is in
effect,
data
is
held
until
the
release
command
is
issued. Also, a
read
of
the data-in
register
does not destroy the information
in
the data-out
register.
Interrupt
Registers
CPT APT GET
END DEC ERR BO
Bl
INTERRUPT STATUS
1
(1R)
INT SPAS LLO
REM
SPASC
LLOC
REMC
ADSC
INTERRUPT STATUS
2 (2R)
CPT
APT GET
END
DEC
ERR BO
Bl
INTERRUPT
MASK
1
(1W)
DMAO
DMAI SPASC LLOC
REMC
ADSC
INTERRUPT
MASK
2 (2W)
The
8291
can be
configured to
generate an
interrupt to the
microprocessor
upon
the occurrence
of
any
of
12
conditions or events
on
the
GPIB.
Upon
receipt of
an
interrupt, the
microprocessor must
read the Interrupt
Status registers to
determine which event has occurred,
and
then execute the appropriate service routine
(if
necessary).
Each
of
the 12 interrupt status
bits
has a
matching
mask
bit in
the
interrupt
mask
registers.
These
mask
bits
are
used
to select
the events
that
will
cause
the
INT pinto be
asserted. Writing a logic "1"
into
any
of these
bits
enables
the
corresponding
interrupt status
bits
to
generate an
interrupt. Bits
in
the Interrupt Status registers
are
set
regardless
of
the states of
the
mask
bits.
The
Interrupt
Status registers are
then cleared
upon
being
read or
when
a local
pon (power-on)
message
is
executed.
If
an event occurs while
one
of
the Interrupt
Status
registers
is
being read,
the event
is
typically
held
until after
its
register
is
cleared
and then placed
in
the register.
The mnemonics
for
each
of
the
bits
in
these
registers
and
a
brief
description
of their
respective functions
appears
in
Table
4.
This
table also indicates
how
each
of
the interrupt
bits
is
set.
TABLE
4.
Interrupt
Bits
Indicates
Undefined
Commands
Set by
(TPAS+ LPAS)«SCG«ACDS.MODE
3
Set by
DTAS
Set
by(EOS+EOI)»LACS
Set
by
DCAS
Set
by
TACS«nba»DAORFD
TACS^SWNS
+ SGNS)
Set by
LACS.ACDS
Shows
status of
the
INT
pin
The
device has
been
enabled
for
a
serial poll
The
device
is in
local
lock out
state.
(LWLS+RWLS)
The
device
is
in
a
remote
state.
(REMS+RWLS)
SPAS^PAS
LL(fjSO LLO
Remotej-ocal
Addressed Unaddressed
CPT
APT
GET
END
DEC
ERR
BO
SPASC
LLOC
RLC
ADSC
INT
SPAS
LLO
REM
An
undefined
command
has been
received.
A
secondary address must be passed through
to
the microprocessor
for
recognition.
A
group execute
trigger
has occurred.
An
EOS
or
EOI message
has
been
received.
Device Clear
Active State
has occurred.
Interface error
has occurred; no
listeners
are active.
A
byte has
been
output.
A
byte
has been
input.
These
are status only.
They
will
not
generate
interrupts, nor
do they have corresponding
mask
bits.
Serial Poll
Active State
change
interrupt
Local lock out
change
interrupt.
Remote/Local change
interrupt.
Address
status
change
interrupt.*
*ln
ton
(talk-only)
and
Ion
(listen-only)
modes, no
ADSC
interrupt
is
generated.
8-91
00229A