Intel MCS48 User Manual page 351

8273
FUNCTIONAL
DESCRIPTION
General
The
Intel®
8273
HDLC/SDLC
controller
is
a
microcom-
puter peripheral device which supports
the International
Standards Organization
(ISO)
High
Level
Data
Link
Control (HDLC), and
IBM Synchronous
Data Link Control
(SDLC) communications
protocols. This
controller
minimizes
CPU
software by supporting
a
comprehensive
frame-level instruction
set
and by hardware implemen-
tation of
the low
level
tasks associated with frame
assembly/disassembly and data
integrity.
The
8273 can be
used
in
either
synchronous
or
asynchronous
applications.
In
asynchronous
applications the data
can be program-
med
to
be
encoded/decoded
in
NRZI
code.
The
clock
is
derived from the
NRZI
data using a
digital
phase locked
loop.
The
data transparency
is
achieved by using a
zero-
bit
insertion/deletion
technique.
The
frames are automati-
cally
checked
for errors
during reception by
verifying the
Frame Check Sequence
(FCS); the
FCS
is
automatically
generated and appended
before the
final
flag
in
transmit.
The
8273
recognizes
and can
generate
flags (01111110),
Abort,
Idle,
and
GA
(EOP)
characters.
The
8273 can
assume
either a primary
(control)
or a
secondary
(slave) role.
It
can
therefore be
readily
implemented
in
an
SDLC
loop configuration as
typified
by
the
IBM
3650
Retail
Store
System
by
programming
the
8273
into a one-bit delay
mode.
In
such
a configuration, a
two
wire
pair
can be
effectively
used
for data
transfer
between
controllers
and
loop
stations.
The
digital
phase
locked loop output
pin
can be used by
the loop
station
without the presence
of
an accurate Tx
clock.
Hardware
Description
The
8273
is
packaged
in
a
40
pin DIP.
The
following
is
a
functional description
of
each
pin.
Pin
Name
(No.) I/O Description
Vcc
(40)
+5V
Supply
GND
(20)
Ground
RESET
(4)
I
A
high
signal
on
this pin
will
force
the 8273
to
an
idle state.
The
8273
will
remain
idle until a
command
is
issued by
the
CPU. The
modem
interface output
signals are forc-
ed high. Reset
must
be
true
for
a
minimum
of 10
TCY.
I
The
RD
and
WR
inputs are en-
abled by
the chip select
input.
I/O
The
Data
Bus
lines are bidirec-
tional three-state
lines
which
in-
terface with the system Data
Bus.
I
The
Write
signal
is
used
to
con-
trol
the
transfer of either a
com-
mand
or data
from
CPU
to
the
8273.
RD
(9)
I
The Read
signal
is
used
to con-
trol
the
transfer of either a data
byte or a
status
word
from
the
8273
to
the
CPU.
TxINT
(2)
O
The
Transmitter
interrupt signal
indicates
that the transmitter
logic requires
service.
RxlNT(H)
O
The
Receiver
interrupt signal
in-
dicates
that
the Receiver
logic re-
quires
service.
CS
(24)
DB7-DB0
(19-12)
WR
(10)
8-61
TxDRQ
(6)
O
Requests
a transfer of data be-
tween
memory
and the 8273
for a
transmit operation.
RxRDQ
(8)
O
Requests
a transfer of
data be-
tween
the
8273 and
memory
for
a
receive operation.
TxDACK
(5)
I
The
Transmitter
DMA
acknow-
ledge
signal notifies
the 8273
that
the
TxDMA
cycle
has been
granted.
RxDACK
(7)
I
The
Receiver
DMA
acknowledge
signal
notifies
the
8273
that the
RxDMA
cycle has
been
granted.
A1-A0
(22-21)
I
These two
lines
are
CPU
Inter-
face Register Select
lines.
TxD
(29)
O
This
line
transmits the
serial
data
to the
communication
channel.
TxC
(28)
I
The
transmitter clock
is
used
to
synchronize
the transmit
data.
RxD
(26)
I
This
line receives
serial
data
from
the
communication
channel.
RxC
(27)
I
The
Receiver Clock
is
used
to
synchronize
the receive
data.
32X
CLK
(25)
I
The 32X
clock
is
used
to
provide
clock recovery
when
an asyn-
chronous
modem
is
used.
In
loop
configuration the loop
station
can run without an accurate 1X
clock by using the
32X
CLK
in
conjunction
with the
DPLL
out-
put.
(This pin
must be grounded
when
not
used).
DPLL
(23)
O
Digital
Phase Locked Loop
out-
put can be
tied to
RxC
and/or
TxC when
1X
clock
is
not
avail-
able.
DPLL
is
used
with
32XCLK.
FLAG DET
(1)
O
Flag Detect signals
that
a
flag
(01111110) has been
received by
an
active receiver.
RTS
(35)
O
Request
to
Send
signals that the
8273
is
ready
to
transmit
data.
CTS
(30)
I
Clear
to
Send
signals that the
modem
is
ready
to
accept
data
from
the 8273.
CD
(31)
I
Carrier Detect
signals that the
line
transmission has
started
and
the
8273
may
begin
to
sample
data
on
RxD
line.
PA2-4
(32-34)
I
General purpose
input
ports.
The
logic levels
on
these
lines
can be
Read
by
the
CPU
through
the
Data Bus
Buffer.
PB1-4
(36-39)
O
General purpose output
ports.
The
CPU
can
write these output
lines
through Data Bus
Buffer.
CLK
(3)
I
A
square wave TTL
clock.
00743A