Intel MCS48 User Manual page 245

2111A
FAMILY
A.C.
CHARACTERISTICS FOR
2111A-2 (250 ns
ACCESS
TIME)
READ
CYCLE
T A = 0°C
to
70°C,
V
cc
= 5V
±5%,
unless otherwise specified.
Symbol
Parameter
Min.
T
[11
Typ.
Max.
Unit
Test Conditions
tRC
Read Cycle 250
ns
tA
Access
Time
250
ns t
r
,
t
f
=
20ns
tco
Chip Enable
To
Output 180 ns
Input
Levels
=
0.8V
or
2.0V
tOD
Output
Disable
To
Output 130
ns
Timing
Reference = 1.5V
t DF
I3J Data
Output
to
High
Z
State
180
ns
Load
=
1
TTL
Gate
tfJH
Previous
Read Data
Valid
after
change of Address
40
ns
and
C|_-
100pF.
WRITE CYCLE
Symbol
Parameter Min.
T
t1]
Typ. Max.
Unit Test Conditions
twc
Write Cycle 170
ns
Uw
Write Delay 20
ns
t
r
,
t
f
= 20ns
tew
Chip Enable
To
Write 150
ns
Input Levels
= 0.8V
or
2.0V
tow
Data Setup 150
ns Timing
Reference = 1.5V
*DH
Data Hold
ns
Load
=
1
TTL
Gate
t
WP Write Pulse 150
ns
andC
L
= 100pF.
tWR
Write
Recovery
ns
tos
Output
Disable
Setup 20
ns
[2]
CAPACITANCE
t
a
=
25°c,f
=
1MHz
Symbol
Test
Limits (pF)
TypJH
Max.
C
IN
Input Capacitance
(All
Input
Pins)
V,
N
=
0V
4 8
C|/0 I/O
Capacitance
V|/
D
=
0V
10 15
WAVEFORMS
READ
CYCLE
WRITE CYCLE
IX
CHIP
ENABLES
(CTJ.CE5)
:x
)C
/i
IX
CHIP
ENABLES
(CE,.CE
2
)
OUTPUT
DISABLE
_J
y
«DS
::t:iDK
+-•
•wc
)C
\
/
)c:
/
-HVB-
NOTES:
1.
Typical values are for
T
A
= 25°C
and nominal supply
voltage.
2.
This parameter
is
periodically
sampled and
is
not
100%
tested.
3.
tQF
'S
with respect to the
trailing
edge of CEi
,
CE2,
or
OD,
whichever occurs
first.
7-7