Intel MCS48 User Manual page 270

8212
FUNCTIONAL DESCRIPTION
Data Latch
The
8 flip-flops that
make
up
the data
latch
are
of
a "D"
type design.
The
output
(Q) of the
flip-flop will
follow the
data input (D) while the clock
input (C)
is
high.
Latching
will
occur
when
the clock (C) returns
low.
The
la
tche d data
is
cleared by an asynchrono
us
re
set
input (CLR).
(Note:
Clock
(C)
Overrides Reset (CLR).)
Output
Buffer
The
outputs
of the data latch (Q) are
connected
to3-state,
non-inverting output
buffers.
These
buffers
have
a
common
control line (EN);
this
control
line
either
enables
the buffer to transmit the data
from
the
outputs
of
the data
latch
(Q) or disables the
buffer,
forcing the output
into
a
high
impedance
state. (3-state)
The
high-impedance
state allows the designer
to
connect
the
8212
directly
onto
the microprocessor
bi-directional
data bus.
Control Logic
The
8212 has
control inputs DS1, DS2,
MD
and STB.
These
inputs are used
to control device
selection, data
latching,
output
buffer state
and
service
request
flip-flop.
DS1,
DS2
(Device
Select)
These
2 inputs are used
for
device
selection.
When
DS1
is
low and
DS2
is
high
(DS1
•
DS2)
the device
is
selected.
In
the selected
state
the output
buffer
is
enabled and
the
service request
flip-flop
(SR)
is
asynchronously
set.
MD
(Mode)
This
input
is
used
to
control the
state of
the output
buffer
and
to
determine
the source
of the clock input
(C) to
the
data
latch.
When
MD
is
high (output
mode)
the output buffers are
enabled
and
the
source
of
clock
(C) to
the data
latch
is
from
the device selection
logic
(DS1
•
DS2).
When
MD
is
low
(input
mode)
the outpu
t
buf
fer state
is
determined by
the device selection
logic
(DS1
•
DS2) and
the
source
of
clock
(C) to
the data
latch
is
the
STB
(Strobe)
input.
STB
(Strobe)
This input
is
used
as the clock (C) to the data latch for the
input
mode
MD
=
0)
and
to
synchronously
reset
the
service request
flip-flop
(SR).
Note
that
the
SR
flip-flop
is
negative
edge
triggered.
Service
Request
Flip-Flop
The
(SR)
flip-flop
is
used
to
generate and
control
interrupts
in
m
icro
computer
systems.
It
is
asynchron-
ously
set
by
the
CLR
input (active low).
When
the (SR)
flip-
flop
is
set
it
is in
the non-interrupting
state.
The
output
of the (SR)
flip-flop (Q)
is
connected
to
an
inverting input
of
a
"NOR"
gate.
The
other input
to
the
"NOR"
gate
is
non-inv
ertin g
and
is
connected
to
the
device selectionjogic (DS1
•
DS2).
The
output
of
the
"NOR"
gate (INT)
is
active
low
(interrupting state) for
connection
to active low input
priority
generating
circuits.
SERVICE REQUEST
FF
DEVICE SELECTION
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DATA OUT EQUALS
3STATE
3STATE
DATA LATCH
DATA
LATCH
DATA LATCH
DATA
IN
1
1
DATA
IN
11
1
DATA
IN
CLR - RESETS
DATA
LATCH
SETSSR
FLIP FLOP
(NO
EFFECT ON OUTPUT BUFFER)
CLR
IDS
vDS
2
)
STB •SR INT
|
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•INTERNAL SR
FLIP FLOP
7-32