Intel MCS48 User Manual page 110

INSTRUCTION SET
ORL
BUS,#data
Logical
OR BUS
With Immediate
Mask
(Not
in
8021, 8022)
1000
10
00
d7d6d
5
d4
d3d
2
d-|do
This
is
a 2-cycle instruction.
Data on
the
BUS
port
is
logically
ORed
with
an
immediately-specified
mask.
This
instruction
assumes
prior specification of
an
'OUTL
BUS.A'
instruction.
(BUS)*-
(BUS)
OR
data
Example:
ORBUS:
ORL BUS,#HEXMSK
;'OR'
BUS
CONTENTS
WITH
;MASK
EQUAL VALUE OF SYMBOL
;'HEXMSK'
ORL
Pp, #data Logical
OR
Port
1
or
2 With
Immediate
Mask
(Not
in
8021,8022)
1000 10pp
d 7
d6d5d4
d
3
d2dido
This
is
a 2-cycle instruction.
Data on
port
'p'
is
logically
ORed
with
an immediately-specified
mask.
(Pp)-*- (Pp)
OR
data
p=1-2
Example:
ORP1:
ORL
P1,
#0FFH
;'OR'
PORT
1
CONTENTS WITH
;MASK
'FP
HEX
(
SET
PORT
1
;TO
ALL ONES)
ORLD
Pp,A
Logical
OR
Port 4-7 With
Accumulator
Mask
1000
1 1
pp
This
is
a 2-cycle instruction.
Data on
port
'p'
is
logically
ORed
with the
digit
mask
contained
in
accumulator
bits 0-3.
(Pp)*-
(Pp)
OR
(Ao_g)
p=4-7
Example: ORP7:
ORLD
P7,A
;'OR'
PORT
7
CONTENTS
;WITH
ACC
BITS
0-3
OUTL
P0,A Output Accumulator Data
to
Port (8021,
8022 Only)
1001
0000
OUTL
BUS,A Output Accumulator Data
to
BUS
(Not
in
8021, 8022)
0000
00 10
This
is
a 2-cycle instruction.
Data
residing
in
the
accumulator
is
transferred (written) to
the
BUS
port
and
latched.
The
latched
data remains
valid until
altered by
another
OUTL
instruction.
Any
other instruction
requiring
use
of
the
BUS
port
(except INS) destroys the
contents
of
the
BUS
latch.
This includes
expanded
memory
operations (such as the
MOVX
instruction).
Logical operations
on
BUS
data (AND, OR)
assume
the
OUTL
BUS.A
instruction
has been issued previously.
Does
not
apply
for
I-
OUTL
P0,A
of
8021
,
8022
(BUS)*-
(A)
Example:
OUTLBP:
OUTL
BUS.A
Mnemonics copyright
Intel
Corporation 1976.
;OUTPUT
ACC CONTENTS TO BUS
4-28