Intel MCS48 User Manual page 343

8259A
LTIM BIT
=
EOGE
1= LEVEL
TO OTHER PRIORTY CELLS
EDGE
SENSE
LATCH
y
<
<t
88
tec
3»f
SET
3=
c
rO-
HI
clr
isr
ISR BIT
NON
MASKED
REQ
NOTES
1.
MATTER CLEAR
ACTIVE
ONLY DURING
ICW1
2.
FREEZE/
IS
ACTIVE
DURING
iHTA/
AND POLL
SEQUENCES ONLY
3.
TRUTH TABLE FOR O-LATCH
C
I
D
I
Q
I
OPERATION
Priority Cell
—
Simplified
Logic Diagram
FOLLOW
HOLD
LEVEL TRIGGERED
MODE
This
mode
is
programmed
using
bit
3
in
ICW1.
If
LTIM
='1', an
interrupt
request
will
be recognized by
a
'high' level
on
IR Input,
and
there
is
no need
for
an
edge
detection.
The
interrupt request
must be removed
before the EOI
command
is
issued
or
the
CPU
interrupt
is
enabled
to prevent a
second
interrupt
from
occurring.
The above
figure
shows
a
concep.jal
circuit
to give the
reader an understanding
of the
level
sensitive
and edge
sensitive input
circuitry of the 8259A.
Be
sure
to
note
that
the request
latch
is
a transparent
D
type
latch.
READING THE
8259A
STATUS
The
input status of several
internal registers
can be
read
to
update
the user information on
the system. The
following registers can be
read by issuing a suitable
OCW3
and
reading with RD.
Interrupt
Mask
Register:
8-bit register
whose
content
specifies the
interrupt request
lines
being masked,
acknowledged. The
highest request
level
is
reset
from
the
IRR when
an
interrupt
is
acknowledged.
(Not
affected by
IMR.)
In-Service Register
(ISR): 8-bit register
which
contains
the
priority levels that are
being
serviced.
The
ISR
is
updated
when
an
End
of Interrupt
command
is
issued.
Interrupt
Mask
Register:
8-bit register
which
contains
the
interrupt
request
lines
which
are
masked.
The IRR can be
read when,
prior to
the
RD
pulse, a
WR
pulse
is
issued with
OCW3
(ERIS
=
1
,
RIS
=
0.)
The
ISR can be read
in
a similar
mode
when ERIS=
1,
RIS=1
in
theOCW3.
There
is
no need
to write
an
OCW3
before every status
read operation, as long as
the status read corresponds
with the previous one;
i.e.,
the
8259A "remembers"
whether
the IRR
or
ISR has been
previously selected
by
the
OCW3.
This
is
not true
when
poll
is
used.
After
initialization
the
8259A
is
set to IRR.
For reading
the
IMR,
no
OCW3
is
needed.
The
output
data
bus
will
contain the
IMR
whenever
RD
is
active
and
A0=1.
Polling
overrides status read when P=1, ERIS=1
in
OCW3.
8-53