Pci Configuration Registers (D30:F0) - Intel 6300ESB Datasheet

®
7—Intel 6300ESB ICH
Hub Interface to PCI Bridge
Registers (D30:F0)
The Hub Interface to PCI Bridge resides in PCI Device 30, Function 0 on Bus #0. This
portion of the Intel
PCI and the Hub Interface. The arbitration for the PCI bus is handled by this PCI device.
The PCI decoder in this device must decode the ranges for the Hub Interface. All
register contents will be lost when core well power is removed.
7.1

PCI Configuration Registers (D30:F0)

Note: Registers that are not shown should be treated as Reserved (see
Configuration Map"
Table 146. PCI Configuration Registers (D30:F0) (Sheet 1 of 2)
.
Offset
00-01h
02-03h
04-05h
06-07h
08h
0Ah
0Bh
0Dh
0Eh
18h
19h
1Ah
1Bh
1Ch
1Dh
1E-1Fh
20-21h
22-23h
24-25h
26-27h
30-31h
32-33h
NOTE: Refer to the Intel
the Revision ID register.
November 2007
Order Number: 300641-004US
®
6300ESB ICH implements the buffering and control logic between
for details).
Mnemonic Register Name/Function
VID Vendor ID
DID Device ID
CMD PCI Device Command Register
PD_STS PCI Device Status Register
RID Revision ID
SCC Sub Class Code
BCC Base Class Code
PMLT Primary Master Latency Timer
HEADTYP Header Type
PBUS_NUM Primary Bus Number
SBUS_NUM Secondary Bus Number
SUB_BUS_NUM Subordinate Bus Number
SMLT Secondary Master Latency Timer
IOBASE IO Base Register
IOLIM IO Limit Register
SECSTS Secondary Status Register
MEMBASE Memory Base
MEMLIM Memory Limit
PREF_MEM_BASE Prefetchable Memory Base
PREF_MEM_MLT Prefetchable Memory Limit
IOBASE_HI I/O Base Upper 16 Bits
IOLIMIT_HI I/O Limit Upper 16 Bits
®
6300ESB ICH Specification Update for the most up-to-date value of
7
Section 6.2, "PCI
Default Type
8086h RO
244Eh RO
0001h R/W
0080h R/W
See NOTE: RO
04h RO
06h RO
00h RO
01h RO
00h RO
00h R/W
00h R/W
00h R/W
F0h R/W
00h R/W
0280h R/W
FFF0h R/W
0000h R/W
0000h RO
0000h RO
0000h RO
0000h RO
®
Intel 6300ESB I/O Controller Hub
DS
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