Offset 24H - 27H: Cpba - Ide Command Posting Base Address - Intel 6300ESB Datasheet

9.1.15 Offset 24h - 27h: CPBA – IDE Command Posting
Base Address
Note: The Intel
accesses. This is much more than is needed; by requesting this much space, decoding
may be simplified. In addition to the standard PCI Memory Space Enable bit, the
Command Posting Enable bits in the IDE I/O Configuration register must be set for the
®
Intel 6300ESB ICH to properly decode the accesses to this range.
Table 337. Offset 24h - 27h: CPBA – IDE Command Posting Base Address
31
Device:
24h-27h
Offset:
00000000h
Default Value:
Bits Name
31:1
Base Address
0
9:4 Hardwired Base Address
3 Prefetchable
2:1 Type
RTE – Resource Type
0
Indicator
®
Intel 6300ESB I/O Controller Hub
DS
444
®
6300ESB ICH requests 1 Kbyte of memory space for the Command Posting
Base address of the IDE Command Posting memory space
(aligned to 1 Kbyte).
These bits are hardwired to '0' to indicate that the size of the
range requested is 1 Kbyte.
Hard-wired to '0', indicating that this range is not pre-
fetchable.
Hard-wired to "00", indicating that this range may be mapped
anywhere in 32-bit address space.
This bit is hard-wired to '0', indicating a request for memory
space.
1
Function:
Read/Write
Attribute:
32-bit
Size:
Description
®
Intel 6300ESB ICH—9
Access
R/W
RO
RO
RO
RO
November 2007
Order Number: 300641-004US