Offset D5H: Back_Cntl-Backed Up Control (Lpc I/F-D31:F0) - Intel 6300ESB Datasheet

8.1.24 Offset D5h: BACK_CNTL—Backed Up Control
(LPC I/F—D31:F0)
Table 204. Offset D5h: BACK_CNTL—Backed Up Control (LPC I/F—D31:F0)
31
Device:
D5h
Offset:
0Fh (upon RTCRST# assertion
low)
Default Value:
2Fh (TOP_SWAP strap active)
No
Lockable:
Bits Name
7 Reserved
6 Reserved
TOP_SWAP: Top-Block
5
Swap Mode
CPU_BIST_EN: Enables
4
CPU BIST
FREQ_STRAP[3:0]: CPU
3:0
Frequency Strap
®
Intel 6300ESB I/O Controller Hub
DS
330
Function:
Attribute:
Power Well:
Description
Reserved.
Reserved.
®
0 = The Intel 6300ESB ICH will not invert A16. This bit is
automatically set to 0 by RTCRST#, but not by any other
type of reset.
®
1 = The Intel 6300ESB ICH will invert A16 for cycles going
to the BIOS space in the FWH (but not for cycles to the
Feature Space in the FWH).
®
NOTE: If the Intel 6300ESB ICH is strapped for Top-Swap
(SIU0_DTR# is low at rising edge of PWROK), then
this bit CANNOT be cleared by software. The strap
jumper should be removed and the system rebooted.
0 = Disable.
1 = The INIT# signal will be driven active when CPURST# is
active. INIT# will go inactive with the same timings as
the other CPU I/F signals (Hold Time after CPURST#
inactive). Note that CPURST# is generated by the
memory controller hub, but the Intel
a Hub Interface special cycle that allows the Intel
6300ESB ICH to control the assertion/deassertion of
CPURST#.
NOTE: This bit is in the Resume well and is reset by
RSMRST#, but not by PXPCIRST# nor CF9h writes.
These bits determine the internal frequency multiplier of the
processor. These bits may be reset to 1111 based on an
external pin strap or through the RTCRST# input signal.
Software must program this field based on the processor's
specified frequency. Note that this field is only writable when
the SAFE_MODE bit is cleared to zero, and SAFE_MODE is
only cleared by PWROK rising edge. These bits are in the RTC
well.
0
Read/Write
8-bit
Size:
RTC
®
6300ESB ICH has
®
Order Number: 300641-004US
®
Intel 6300ESB ICH—8
Access
RO
RO
R/W
R/W
R/W
November 2007