Offset 82H: Pci_Mast_Sts-Pci Master Status Register (Hub-Pci-D30:F0); Offset 90H: Err_Cmd-Error Command Register (Hub-Pci-D30:F0) - Intel 6300ESB Datasheet

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7—Intel 6300ESB ICH
7.1.30 Offset 82h: PCI_MAST_STS—PCI Master Status
Register (HUB-PCI—D30:F0)
Table 176. Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI—
D30:F0)
30
Device:
82h
Offset:
00h
Default Value:
Bits Name
Internal South PCI
7 Master Request Status
(INT_MREQ_STS)
6:4 Reserved
PCI Master Request
3:0
Status (PCI_MREQ_STS)
7.1.31 Offset 90h: ERR_CMD—Error Command Register
(HUB-PCI—D30:F0)
Note: This register configures the Intel
system errors. The actual assertion of the internal SERR# (routed to cause NMI# or
SMI#) is enabled through the PCI Command register.
Table 177. Offset 90h: ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
30
Device:
90h
Offset:
00h
Default Value:
No
Lockable:
Bits Name
7:3 Reserved
SERR# Enable on
2 Receiving Target Abort
(SERR_RTA_EN)
1:0 Reserved
November 2007
Order Number: 300641-004US
Attribute:
Description
Allows software to see if the internal DMA controller or LPC
has requested use of the PCI bus.
0 = Software clears this bit by writing a'1'to the bit position.
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1 = The Intel 6300ESB ICH's internal DMA controller or LPC
has requested use of the PCI bus.
Reserved.
Allows software to see if a particular bus master has
requested use of the PCI bus.
0 = Software clears these bits by writing a 1 to the bit
position.
1 = The associated PCI master has requested use of the PCI
bus.
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6300ESB ICH's Device 30 responses to various
Attribute:
Power Well:
Description
Reserved.
0 = Disable.
1 = Enable. When SERR_EN is set, the Intel
will report SERR# when SERR_RTA is set.
Reserved. Bit 1 was the SERR# Enabled for Delayed
Transaction Timeout, see Section 7.1.24, "Offset 3E - 3Fh:
BRIDGE_CNT—Bridge Control Register
0
Function:
Read/Write Clear
8-bit
Size:
0
Function:
Read/Write
8-bit
Size:
Core
®
6300ESB ICH
(HUB-PCI—D30:F0)".
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