16.4.15 Offset 60 - 61H: Wdt Configuration Register; 16.4.16 Offset 68H: Wdt Lock Register - Intel 6300ESB Datasheet

®
16—Intel 6300ESB ICH

16.4.15 Offset 60 - 61h: WDT Configuration Register

Table 550. Offset 60 - 61h: WDT Configuration Register
29
Device:
60 - 61h
Offset:
00h
Default Value:
No
Lockable:
Bits Name
15:6 Reserved
WDT_OUTPUT: Output
5
Enable
4:3 Reserved
WDT_PRE_SEL:
2
Prescaler Select
1:0 WDT_INT_TYPE

16.4.16 Offset 68h: WDT Lock Register

November 2007
Order Number: 300641-004US
Attribute:
Power Well:
Description
Reserved.
This bit indicates whether or not the WDT will toggle the
external WDT_TOUT# pin when the WDT times out.
0 = Enabled (Default)
1 = Disabled
This signal is muxed with GPIO32.
Reserved.
The WDT provides two options for prescaling the main down-
counter. The preload values are loaded into the main down-
counter right justified. The prescaler adjusts the starting
point of the 35-bit down counter.
0 = The 20-bit Preload Value is loaded into bits 34:15 of the
main down counter. The resulting timer clock is the PCI
Clock (33 MHz) divided by 2
generated is 1 KHz, (Default)
1 = The 20-bit Preload Value is loaded into bits 24:5 of the
main down counter. The resulting timer clock is the PCI
Clock (33 MHz) divided by 2
generated is 1 MHz.
NOTE: Timeout value is determined by the preload value
multiplied by the clock period.
The WDT timer supports programmable routing of interrupts.
The set of bits allows the user to choose the type of interrupt
desired when the WDT reached the end of the first stage
without being reset.
00 = IRQ (APIC 1, INT 10) (Default)
01 = Reserved
10 = SMI
11 = Disabled
IRQ is Active low, level triggered
4
Function:
Read, Write
16-bit
Size:
Core
15
. The approximate clock
5
. The approximate clock
Intel
Access
RO
R/W
RO
R/W
R/W
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