Intel 6300ESB Datasheet page 28
I/o controller hub
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Also See for 6300ESB:
- User manual (38 pages) ,
- Design manual (14 pages) ,
- Design manual (320 pages)
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19.5.1.3 Internal Register Descriptions ................................................... 710
19.5.1.4 FIFO Operation ....................................................................... 723
19.6
Logical Device 7 (07H): Port 60/64 Emulation...................................................... 724
19.6.1 Feature List ......................................................................................... 724
19.6.2 Overview ............................................................................................. 724
19.6.2.1 Port 60H Emulation (SCR60) ..................................................... 725
19.6.2.2 Port 64H Emulation (SCR64) ..................................................... 725
19.7
Serial IRQ....................................................................................................... 725
19.7.1 Timing Diagrams For SIU_SERIRQ Cycle .................................................. 725
19.7.1.1 SIU_SERIRQ Cycle Control ....................................................... 726
19.7.1.2 SIU_SERIRQ Data Frame.......................................................... 727
19.7.1.3 Stop Cycle Control................................................................... 727
19.7.1.4 Latency.................................................................................. 728
19.7.1.5 EOI/ISR Read Latency.............................................................. 728
19.7.1.6 Reset and Initialization............................................................. 728
19.8
Configuration .................................................................................................. 728
19.8.1 Configuration Port Address Selection ....................................................... 728
19.8.2 Primary Configuration Address Decoder ................................................... 728
19.8.2.1 Entering the Configuration State ............................................... 729
19.8.2.2 Exiting the Configuration State.................................................. 729
19.8.2.3 Configuration Sequence ........................................................... 729
19.8.3 SIU Configuration Registers Summary ..................................................... 730
19.8.3.1 Global Control/Configuration Registers [00h - 2Fh]..................... 731
19.8.3.2 Logical Device Configuration Registers [30h - FFh] ..................... 731
20
Serial ATA Controller Registers
(D31:F2)737
20.1
PCI Configuration Registers (SATA-D31:F2) ........................................................ 737
20.1.1 Offset 00 - 01h: VID-Vendor ID Register (SATA-D31:F2) ........................ 738
20.1.2 Offset 02 - 03h: DID-Device ID Register (SATA-D31:F2)......................... 739
20.1.3 Offset 04h - 05h: CMD-Command Register (SATA-D31:F2)....................... 739
20.1.4 Offset 06 - 07h: STS-Device Status Register
(SATA-D31:F2) .................................................................................... 741
20.1.5 Offset 09h: PI-Programming Interface (SATA-D31:F2)............................. 742
20.1.6 Offset 0Ah: SCC-Sub Class Code (SATA-D31:F2) .................................... 742
20.1.7 Offset 0Bh: BCC-Base Class Code (SATA-D31:F2) ................................... 743
20.1.8 Offset 0Dh: MLT-Master Latency Timer (SATA-D31:F2) ............................ 743
20.1.9 Offset 10h - 13h: PCMD_BAR-Primary Command Block
Base Address Register (SATA-D31:F2) .................................................... 744
20.1.10Offset 14h - 17h: PCNL_BAR-Primary Control Block Base
Address Register (SATA-D31:F2)............................................................ 744
20.1.11Offset 18h - 1Bh: SCMD_BAR-Secondary Command Block
Base Address Register (IDE D31:F1) ....................................................... 745
20.1.12Offset 14h - 17h: SCNL_BAR-Secondary Control Block
Base Address Register (IDE D31:F1) ....................................................... 745
20.1.13Offset 20h - 23h: BAR-Legacy Bus Master Base Address
20.1.14Offset 2Ch - 2Dh: SVID-Subsystem Vendor ID
(SATA-D31:F2) .................................................................................... 746
20.1.15Offset 2Eh - 2Fh: SID-Subsystem ID (SATA-D31:F2)............................... 747
20.1.16Offset 34h: CAP-Capabilities Pointer Register
(SATA-D31:F2) .................................................................................... 747
20.1.17Offset 3Ch: INTR_LN-Interrupt Line Register
(SATA-D31:F2) .................................................................................... 747
20.1.18Offset 3Dh: INTR_PN-Interrupt Pin Register
(SATA-D31:F2) .................................................................................... 748
®
Intel
6300ESB I/O Controller Hub
DS
28
®
Intel
6300ESB ICH-Contents
November 2007
Order Number: 300641-004US
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