Smbus Slave Interface - Intel 6300ESB Datasheet

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5—Intel 6300ESB ICH
Table 130. Enables for the Host Notify Command
HOST_NOTIFY_INTREN
(Slave Control I/O
Register, Offset 11h, bit
0)
0
X
1
1
5.19.6 SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enabled and the signal is asserted,
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the Intel
S4.
Note: Any event on SMBALERT# (regardless whether it is programmed as a GPIO or not),
causes the event message to be sent in "heartbeat mode."
5.19.7 SMBus CRC Generation and Checking
When the AAC bit is set in the Auxiliary Control register, the Intel
automatically calculate and drive CRC at the end of the transmitted packet for write
cycles, and will check the CRC for read cycles. It will not transmit the contents of the
PEC register for CRC. The PEC bit must not be set in the Host Control register when this
bit is set, or unspecified behavior will result.
When the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch will be set.
5.19.8

SMBus Slave Interface

The Intel
signals. The SMBus slave logic will not generate or handle receiving the PEC byte and
will only act as a Legacy Alerting Protocol (Alert on LAN*) device. The slave interface
allows the Intel
to perform specific actions. Key features and capabilities include:
•
Supports decode of three types of messages: Byte Write, Byte Read, and Host
Notify
•
Receive Slave Address register: This is the address that the Intel
decodes. A default value is provided so that the slave interface may be used
without the processor having to program this register.
•
Receive Slave Data register in the SMBus I/O space that includes the data written
by the external microcontroller
•
Registers that the external microcontroller may read to get the state of the Intel
6300ESB ICH. See
•
Status bits to indicate that the SMLink/SMBus slave logic caused an interrupt or
SMI# due to the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command.
November 2007
Order Number: 300641-004US
SMB_SMI_EN (Host
Config Register,
D31:F3:Off40h, Bit 1)
X
X
0
1
6300ESB ICH may generate an interrupt, an SMI# or a wake event from S1
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6300ESB ICH's SMBus Slave interface is accessed through the SMLINK[1:0]
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6300ESB ICH to decode cycles, and allows an external microcontroller
Table 135.
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11h, bit
1)
0
1
X
X
Intel
Result
None
Wake generated
Interrupt generated
Slave SMI# generated
(SMBUS_SMI_STS)
–
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6300ESB ICH will
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6300ESB ICH
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6300ESB I/O Controller Hub
DS
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