Usb Legacy Keyboard/Mouse Control Register Bit Implementation - Intel 6300ESB Datasheet

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5—Intel 6300ESB ICH
5.17.9 USB Legacy Keyboard Operation
Typically when a USB keyboard is plugged into the system, and a standard keyboard is
not, the system may not boot, and DOS legacy software will not run, because the
keyboard will not be identified. In an Intel
will allow the USB keyboard and DOS legacy software to run. Port 60/64 emulation
registers may be enabled by BIOS typically in a pre-OS environment and may be
disabled during run time.
The Intel
accesses that typically go to the keyboard controller and put the expected data from
the USB keyboard into ports 60/64.
The following table summarizes the implementation of the bits in the USB Legacy
Keyboard/Mouse Control Registers.
Table 105. USB Legacy Keyboard/Mouse Control Register Bit Implementation
(Sheet 1 of 2)
Bit
Bit Name
#
SMI Caused by
15 End of Pass-
Through
PCI Interrupt
13
Enable
SMI Caused by
12
USB Interrupt
SMI Caused by
11
Port 64 Write
SMI Caused by
10
Port 64 Read
SMI Caused by
9
Port 60 Write
SMI Caused by
8
Port 60 Read
SMI at End of
7 Pass-Through
Enable
Pass Through
6
State
A20Gate Pass-
5
Through Enable
November 2007
Order Number: 300641-004US
®
6300ESB ICH implements a series of trapping operations that will snoop
Summary
Note this bit in all host controllers will be set at the same time and
Logically 1 bit
cleared at the same time. It is cleared whenever software writes a
for all
one to this bit in any of the three host controllers. This bit may either
controllers
be implemented separately for each controller or shared and aliased.
Independent
Each bit provides individual host control.
enable
Independent
Individual status bits for each controller.
status
Note this bit in all host controllers will be set at the same time and
Logically 1 bit
cleared at the same time. It is cleared whenever software writes a
for all
one to this bit in any of the three host controllers. This bit may either
controllers
be implemented separately for each controller or shared and aliased.
Note this bit in all host controllers will be set at the same time and
Logically 1 bit
cleared at the same time. It is cleared whenever software writes a
for all
one to this bit in any of the three host controllers. This bit may either
controllers
be implemented separately for each controller or shared and aliased.
Note this bit in all host controllers will be set at the same time and
Logically 1 bit
cleared at the same time. It is cleared whenever software writes a
for all
one to this bit in any of the three host controllers. This bit may either
controllers
be implemented separately for each controller or shared and aliased.
Note this bit in all host controllers will be set at the same time and
Logically 1 bit
cleared at the same time. It is cleared whenever software writes a
for all
one to this bit in any of the three host controllers. This bit may either
controllers
be implemented separately for each controller or shared and aliased.
This bit enables the generation of the SMI based on bit 15 within the
Separate
same function. When bit 15 is implemented as a shared/aliased bit
enables ORed
across all functions, the bit 7's from all three controllers are ORed
together
together and used to enable the SMI based on bit 15.
Logically 1 bit This bit in all host controllers reflects the state of the Pass-Through
for all state machine. Software may force this bit to zero by clearing the
controllers A20Gate Pass-Through Enable (bit 5) in all of the host controllers.
When any of these bits in the three host controllers is set, the Intel
ORed together
6300ESB ICH will enable the Legacy Keyboard A20Gate Pass-through
to enable the
sequence. This prevents the SMI status bits (11:8) from asserting in
pass-through
all three controllers when the specific sequence of I/O cycles is
state machine
observed.
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6300ESB ICH system Port 60/64 emulation
Details
®
Intel
®
6300ESB I/O Controller Hub
DS
217