System Management Tco Registers (D31:F0) - Intel 6300ESB Datasheet

Table 300. BUS_CYC_TRACK— Bus Cycle Tracker
31
Device:
PMBASE +4Eh
I/O Address:
No
Lockable:
Bits Name
7:4
3:0
8.9 System Management TCO Registers
(D31:F0)
The TCO logic is accessed through registers mapped to the PCI configuration space
(Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers,
see LPC Device 31:Function 0 PCI Configuration registers.
8.9.1 TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which
is, ACPIBASE + 60h in the PCI config space. The following table shows the mapping of
the registers within that 32-byte range. Each register is described in the sections
below.
Table 301. TCO I/O Register Map
Offset
00h
01h
02h
03h
04h - 05h
06h - 07h
08h - 09h
0Ah - 0Bh
0Ch - 0Dh
0Eh
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Intel 6300ESB I/O Controller Hub
DS
416
Corresponds to the byte enables, as would be defined by the
PCI C/BE# signals on the PCI bus (even though it may not be
a real PCI cycle). The value is latched based on SMI# going
active.
Corresponds to the cycle type, as would be defined by the PCI
C/BE# signals on the PCI bus (even though it may not be a
real PCI cycle). The value is latched based on SMI# going
active.
Typ
e
R/W TCO_RLD: TCO Timer Reload and Current Value
R/W TCO_TMR: TCO Timer Initial Value
R/W TCO_DAT_IN: TCO Data In
R/W TCO_DAT_OUT: TCO Data Out
R/W TCO1_STS: TCO Status
R/W TCO2_STS: TCO Status
R/W TCO1_CNT: TCO Control
R/W TCO2_CNT: TCO Control
TCO_MESSAGE1, TCO_MESSAGE2: Used by BIOS to indicate POST/Boot
R/W
progress
R/W TCO_WDSTATUS: Watchdog Status Register
0
Function:
Read-Only
Attribute:
8-bit
Size:
Core
Power Well:
Description
Register Name: Function
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Intel 6300ESB ICH—8
Access
November 2007
Order Number: 300641-004US