Intel 6300ESB Datasheet page 12

5.14.2.2 IDE Port Decode...................................................................... 179
5.14.2.3 IDE Legacy Mode and Native Mode ............................................ 179
5.14.2.4 PIO IDE Timing Modes ............................................................. 180
5.14.2.5 IORDY Masking ....................................................................... 181
5.14.2.6 PIO 32-Bit IDE Data Port Accesses............................................. 181
5.14.2.7 PIO IDE Data Port Prefetching and Posting .................................. 181
5.14.3 Bus Master Function.............................................................................. 182
5.14.3.1 Physical Region Descriptor Format ............................................. 182
5.14.3.2 Line Buffer ............................................................................. 183
5.14.3.3 Bus Master IDE Timings ........................................................... 183
5.14.3.4 Interrupts .............................................................................. 183
5.14.3.5 Bus Master IDE Operation ........................................................ 184
5.14.3.6 Error Conditions ...................................................................... 185
5.14.3.7 8237-Like Protocol .................................................................. 185
5.14.4 Ultra ATA/33 Protocol ............................................................................ 186
5.14.4.1 Signal Descriptions .................................................................. 186
5.14.4.2 Operation............................................................................... 187
5.14.4.3 CRC Calculation ...................................................................... 187
5.14.5 Ultra ATA/66 Protocol ............................................................................ 188
5.14.6 Ultra ATA/100 Protocol .......................................................................... 188
5.14.7 Ultra ATA/33/66/100 Timing .................................................................. 188
5.15 SATA Host Controller (D31:F2) .......................................................................... 189
5.15.1 Overview ............................................................................................. 189
5.15.2 Theory of Operation .............................................................................. 189
5.15.2.1 Standard ATA Emulation........................................................... 189
5.15.2.2 48-bit LBA Operation (Logical Block Addressing) .......................... 189
5.15.3 Hot Plug Operation................................................................................ 189
5.15.4 Power Management Operation ................................................................ 189
5.15.4.1 Power State Mappings.............................................................. 190
5.15.4.2 Power State Transitions............................................................ 191
5.15.4.3 SMI Trapping (APM)................................................................. 191
5.15.5 SATA Interrupts.................................................................................... 192
5.15.6 SATALED# ........................................................................................... 192
5.16 Multimedia Event Timers................................................................................... 192
5.16.1 Overview ............................................................................................. 192
5.16.2 Timer Accuracy .................................................................................... 193
5.16.3 Interrupt Mapping................................................................................. 193
5.16.4 Periodic vs. Non-Periodic Modes.............................................................. 193
5.16.5 Enabling the Timers .............................................................................. 195
5.16.6 Interrupt Levels.................................................................................... 195
5.16.7 Handling Interrupts............................................................................... 195
5.16.8 Issues Related to 64-bit Timers with 32-bit Processors............................... 195
5.17 USB UHCI Controllers (D29:F0 and F1) ............................................................... 196
5.17.1 Overview ............................................................................................. 196
5.17.2 Data Structures in Main Memory ............................................................. 196
5.17.2.1 Frame List Pointer ................................................................... 196
5.17.2.2 Transfer Descriptors (TD) ......................................................... 197
5.17.2.3 Queue Head (QH).................................................................... 201
5.17.3 Data Transfers to/from Main Memory ...................................................... 202
5.17.3.1 Executing the Schedule ............................................................ 202
5.17.3.2 Processing Transfer Descriptors................................................. 203
5.17.3.3 Command Register, Status Register, and TD Status Bit Interaction 204
5.17.3.4 Transfer Queuing .................................................................... 204
5.17.4 Data Encoding and Bit Stuffing ............................................................... 208
5.17.5 Bus Protocol......................................................................................... 208
5.17.5.1 Bit Ordering............................................................................ 208
5.17.5.2 SYNC Field ............................................................................. 208
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Intel 6300ESB I/O Controller Hub
DS
12
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Intel 6300ESB ICH-Contents
November 2007
Order Number: 300641-004US