Offset D4H: Gen_Sta-General Status (Lpc I/F-D31:F0) - Intel 6300ESB Datasheet

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8—Intel 6300ESB ICH
Table 202. Offset D0h - D3h: GEN_CNTL—General Control Register (LPC I/F—
D31:F0)
(Sheet 3 of 3)
31
Device:
D0h - D3h
Offset:
00000080h
Default Value:
No
Lockable:
Bits Name
DCB_EN: DMA Collection
2
Buffer Enable
DTE: Delayed
1
Transaction Enable
0 POS_DEC_EN
8.1.23 Offset D4h: GEN_STA—General Status (LPC I/F—
D31:F0)
Table 203. Offset D4h: GEN_STA—General Status (LPC I/F—D31:F0)
31
Device:
D4h
Offset:
0Xh
Default Value:
No
Lockable:
Bits Name
7:3 Reserved
2 SAFE_MODE
1 NO_REBOOT
0 Reserved
November 2007
Order Number: 300641-004US
Attribute:
Power Well:
Description
0 = DCB disabled.
1 = Enables DMA Collection Buffer (DCB) for LPC I/F and PC/
PCI DMA.
0 = Delayed transactions disabled.
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1 = The Intel 6300ESB ICH enables delayed transactions for
internal register, FWH and LPC I/F accesses.
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0 = The Intel 6300ESB ICH will perform subtractive decode
on the PCI bus and forward the cycles to LPC if not to an
internal register or other known target on LPC. Accesses
to internal registers and to known LPC devices will still be
positively decoded.
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1 = Enables Intel 6300ESB ICH to only perform positive
decode on the PCI bus. This must be selected when the
PCI to ISA (subtractive docking bridge) is used.
Attribute:
Power Well:
Description
Reserved.
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0 = The Intel 6300ESB ICH sampled AC_SDOUT low on the
rising edge of PWROK.
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1 = The Intel 6300ESB ICH sampled AC_SDOUT high on the
rising edge of PWROK.
0 = Normal TCO Timer reboot functionality (reboot after 2nd
TCO timeout). This bit cannot be set to 0 by software
when the strap is set to No Reboot.
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1 = The Intel 6300ESB ICH will disable the TCO Timer
system reboot feature. This bit is set either by hardware
when SPKR is sampled high on the rising edge of PWROK,
or by software writing a 1 to the bit.
Reserved.
0
Function:
Read/Write
32-bit
Size:
Core
0
Function:
Read/Write
8-bit
Size:
Core
Intel
Access
R/W
R/W
Access
RO
R/W
(special)
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6300ESB I/O Controller Hub
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