Intel 6300ESB Datasheet page 406

Table 292. SMI_EN—SMI Control and Enable Register (Sheet 2 of 3)
31
Device:
PMBASE + 30h
I/O Address:
00000000h
Default Value:
No
Lockable:
Bits Name
14 PERIODIC_EN
13 TCO_EN
12 Reserved
MCSMI_EN: Microcon-
11
troller SMI Enable
10:8 Reserved
BIOS_RLS: BIOS
7
Release
SWSMI_TMR_EN:
6 Software SMI# Timer
Enable
5 APMC_EN
4 SLP_SMI_EN
3 LEGACY_USB_EN
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Intel 6300ESB I/O Controller Hub
DS
406
Attribute:
Power Well:
Description
0 = Disable.
®
1 = Enables the Intel 6300ESB ICH to generate an SMI#
when the PERIODIC_STS bit is set in the SMI_STS
register.
0 = Disables TCO logic generating an SMI#. Note that when
the NMI2SMI_EN bit is set, SMIs that are caused by re-
routed NMIs will not be gated by the TCO_EN bit. Even
when the TCO_EN bit is 0, NMIs will still be routed to
cause SMIs.
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit can not be written once the TCO_LOCK bit (at
offset 08h of TCO I/O Space) is set. This prevents
unauthorized software from disabling the generation
of TCO-based SMI's
Reserved.
0 = Disable.
®
1 = Enables the Intel 6300ESB ICH to trap accesses to the
microcontroller range (62h or 66h) and generate an
SMI#. Note that "trapped' cycles will be claimed by the
®
Intel 6300ESB ICH on PCI, but not forwarded to LPC.
Reserved.
0 = This bit will always return 0 on reads. Writes of 0 to this
bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI
software when a one is written to this bit position by
BIOS software.
0 = Disable. Clearing the SWSMI_TMR_EN bit before the
timer expires will reset the timer and the SMI# will not
be generated.
1 = Starts Software SMI# Timer. When the SWSMI timer
expires (the timeout period depends upon the
SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set
and an SMI# is generated. SWSMI_TMR_EN stays set
until cleared by software.
0 = Disable. Writes to the APM_CNT register will not cause an
SMI#.
1 = Enables writes to the APM_CNT register to cause an
SMI#.
0 = Disables the generation of SMI# on SLP_EN. Note that
this bit must be 0 before the software attempts to
transition the system into a sleep state by writing a 1 to
the SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT
register) will generate an SMI#, and the system will not
transition to the sleep state based on that write to the
SLP_EN bit.
0 = Disable.
1 = Enables legacy USB circuit to cause SMI#.
0
Function:
Read/Write
32-bit
Size:
Core
Order Number: 300641-004US
®
Intel 6300ESB ICH—8
Access
R/W
R/W
R/W
WO
R/W
R/W
R/W
R/W
November 2007