Pci Message-Based Interrupts - Intel 6300ESB Datasheet

Table 53. Remote Read Message (Sheet 2 of 2)
Cycle
37
38
39
NOTE: Cycle 21 through 36 contain the remote register data. The status information in cycle 37
specifies when the data is valid or invalid. Remote read cycle is always successful
(although the data may be valid or invalid) in that it is never retried. The reason for this
is that Remote Read is a debug feature, and a "hung" remote APIC that is unable to
respond should not cause the debugger to hang.
5.7.6

PCI Message-Based Interrupts

5.7.6.1 Theory of Operation
The following scheme is only supported when the internal I/O(x) APIC is used, rather
than just the 8259.
The Intel
as write cycles rather than using the traditional PIRQ[A:D] signals. Essentially, the PCI
devices are given a write path directly to a register that will cause the desired interrupt.
This mode is only supported when the Intel
enabled. Upon recognizing the write from the peripheral, the Intel
send the interrupt message to the processor using the I/O APIC's serial bus.
The interrupts associated with the PCI Message-based interrupt method must be set up
for edge triggered mode, rather than level triggered, since the peripheral only does the
write to indicate the edge.
The following sequence is used:
1. During PCI PnP, the PCI peripheral is first programmed with an address
(MESSAGE_ADDRESS) and data value (MESSAGE_DATA) that will be used for the
interrupt message delivery. For the Intel
is the IRQ Pin Assertion Register, which is mapped to memory location:
FEC0_0020h.
2. To cause the interrupt, the PCI peripheral requests the PCI bus and when granted,
writes the MESSAGE_DATA value to the location indicated by the
MESSAGE_ADDRESS. The MESSAGE_DATA value indicates which interrupt
occurred. This MESSAGE_DATA value is a binary encoded. For example, to indicate
that interrupt 7 should go active, the peripheral will write a binary value of
0000111. The MESSAGE_DATA will be a 32-bit value, although only the lower 5 bits
are used.
3. When the PRQ bit in the APIC Version Register is set, the Intel
positively decodes the cycles (as a slave) in Medium time.
4. The Intel
and sets the appropriate IRR bit in the internal I/O APIC. The corresponding
interrupt must be set up for edge-triggered interrupts. The Intel
supports interrupts 00h through 23h. Binary values outside this range will not
cause any action.
5. After sending the interrupt message to the processor, the Intel
automatically clear the interrupt.
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Intel 6300ESB I/O Controller Hub
DS
132
Bit 1 Bit 0
S S
C C
1 1
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6300ESB ICH supports the new method for PCI devices to deliver interrupts
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6300ESB ICH decodes the binary value written to MESSAGE_ADDRESS
Comments
Data Status: 00 = valid, 11 = invalid
Check Sum for data d31-d00
Idle
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6300ESB ICH's internal I/O APIC is
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6300ESB ICH, the MESSAGE_ADDRESS
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Intel 6300ESB ICH—5
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6300ESB ICH will
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6300ESB ICH
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6300ESB ICH
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6300ESB ICH will
November 2007
Order Number: 300641-004US