Enabling The Timers - Intel 6300ESB Datasheet

®
5—Intel 6300ESB ICH
5.16.5

Enabling the Timers

The BIOS or OS PnP code should route the interrupts. This includes the Legacy Rout bit,
Interrupt Rout bit (for each timer), interrupt type (to select the edge or level type for
each timer)
The Device Driver code should do the following for an available timer:
1. Set the Overall Enable bit (Offset 04h, bit 0).
2. Set the timer type field (selects one-shot or periodic).
3. Set the interrupt enable.
4. Set the comparator value.
5.16.6 Interrupt Levels
Interrupts directed to the internal 8259s are active high. See
Interrupt Controller (APIC) (D29:F5)"
programming of the
I/O APIC for detecting internal interrupts. When the interrupts are mapped to the I/O
APIC and set for level-triggered mode, they may be shared with PCI interrupts,
although it is unlikely for the OS to attempt this. When more than one timer is
configured to share the same IRQ using the TIMERn_INT_ROUT_CNF fields, the
software must configure the timers to level-triggered mode. Edge-triggered interrupts
cannot be shared.
5.16.7 Handling Interrupts
When each timer has a unique interrupt and the timer has been configured for edge-
triggered mode, no specific steps are required. No read is required to process the
interrupt.
When a timer has been configured to level-triggered mode, its interrupt must be
cleared by the software. This is done by reading the interrupt status register and
writing a 1 back to the bit position for the interrupt to be cleared.
Independent of the mode, software may read the value in the main counter to see how
much time has passed between when the interrupt was generated and when it was first
serviced.
When Timer 0 is set up to generate a periodic interrupt, the software may check to see
how much time remains until the next interrupt by checking the timer value register.
5.16.8 Issues Related to 64-bit Timers with 32-bit
Processors
A 32-bit timer may be read directly using processors that are capable of 32-bit or 64-
bit instructions. However, a 32-bit processor may not be able to directly read 64-bit
timer. A race condition comes up when a 32-bit processor reads the 64-bit register
using two separate 32-bit reads. The danger is that just after reading one half, the
other half rolls over and changes the first half.
When a 32-bit processor needs to access a 64-bit timer, it must first halt the timer
before reading both the upper and lower 32-bits of the timer.
November 2007
Order Number: 300641-004US
for information regarding the polarity
Intel
Section 5.7, "Advanced
®
6300ESB I/O Controller Hub
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DS