Power Sequencing And Reset Signal Timings - Intel 6300ESB Datasheet

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22—Intel 6300ESB ICH
Table 727. Power Sequencing and Reset Signal Timings
Sym
t170 VccRTC active to RTCRST# inactive
t171 V5RefSus active to VccSus3_3, VccSus1_5 active
t172 VccRTC supply active to VccSus supplies active
t173 VccSus supplies active to RSMRST# inactive
t174 V5Ref active to Vcc3_3, Vcc1_5, VccHI active
VccSus supplies active to Vcc3_3, Vcc1_5, VccHI
t175
supplies active
t176 Vcc3_3, Vcc1_5, VccHI supplies active to PWROK.
t177 PWROK active to SUS_STAT# inactive
t178 SUS_STAT# inactive to PXPCIRST# inactive
t179 AC_RST# active low pulse width
t180 AC_RST# inactive to BIT_CLK startup delay
NOTES:
1. The V5Ref supply must power up before or simultaneous with its associated 3.3 V supply, and must power
down simultaneous with or after the 3.3 V supply. See the Intel
2. The associated 3.3 V and 1.5 V supplies must power up or down simultaneously.
3. The VccSus supplies must never be active while the VccRTC supply is inactive.
4. SYSRESET# is not checked for PWROK transitions (t177).
November 2007
Order Number: 300641-004US
Parameter Min Max Units
5 - ms
0 - ms
0 - ms
10 - ms
0 - ms
0 - ms
99 - ms
32 38 RTCCLK
1 3 RTCCLK
1 us
162.8 ns
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6300ESB ICH Design Guide for details.
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Intel 6300ESB I/O Controller Hub
Notes Fig
Figure 61
1, 2 Figure 61
3 Figure 61
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Figure 62
1, 2 Figure 61
3 Figure 61
Figure 61
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