Dma Request Assertion Through Ldrq; Abandoning Dma Requests - Intel 6300ESB Datasheet

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5—Intel 6300ESB ICH
LDRQ# is synchronous with LCLK (PCI clock). As shown in
uses the following serial encoding sequence:
•
Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high
during idle conditions.
•
The next 3 bits contain the encoded DMA channel number (MSB first).
•
The next bit (ACT) indicates whether the request for the indicated DMA channel is
active or inactive. The ACT bit will be a 1 (high) to indicate when it is active and 0
(low) when it is inactive. The case where ACT is low will be rare, and is only used to
indicate that a previous request for that channel is being abandoned.
•
After the active/inactive indication, the LDRQ# signal must go high for at least 1
clock. After that one clock, LDRQ# signal may be brought low to the next encoding
sequence.
When another DMA channel also needs to request a transfer, another sequence may be
sent on LDRQ#. For example, if an encoded request is sent for channel 2, and then
channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the
peripheral may send the encoded request for channel 3. This allows multiple DMA
agents behind an I/O device to request use of the LPC interface, and the I/O device
does not need to self-arbitrate before sending the message.
Figure 12. DMA Request Assertion Through LDRQ#
LCLK
LDRQ#
5.4.2

Abandoning DMA Requests

DMA Requests may be deasserted in two fashions: on error conditions by sending an
LDRQ# message with the 'ACT' bit set to '0', or normally through a SYNC field during
the DMA transfer. This section describes boundary conditions where the DMA request
needs to be removed prior to a data transfer.
There may be some special cases where the peripheral desires to abandon a DMA
transfer. The most likely case of this occurring is due to a floppy disk controller which
has overrun or underrun its FIFO, or software stopping a device prematurely.
In these cases, the peripheral wishes to stop further DMA activity. It may do so by
sending an LDRQ# message with the ACT bit as '0'. However, since the DMA request
was seen by the Intel
granted and will shortly run on LPC. Therefore, peripherals must take into account that
a DMA cycle may still occur. The peripheral may choose not to respond to this cycle, in
which case the host will abort it, or it may choose to complete the cycle normally with
any random data.
This method of DMA deassertion should be prevented whenever possible, to limit
boundary conditions both on the Intel
November 2007
Order Number: 300641-004US
Start MSB
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6300ESB ICH, there is no ensuring that the cycle has not been
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6300ESB ICH and the peripheral.
Figure 12 the peripheral
LSB ACT
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Intel 6300ESB I/O Controller Hub
Start
DS
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