Offset 3Dh: Intr_Pn-Interrupt Pin Register (Audio-D31:F5); Offset 40H: Pcid-Programmable Codec Id Register (Audio-D31:F5) - Intel 6300ESB Datasheet

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13—Intel 6300ESB ICH
13.1.18 Offset 3Dh: INTR_PN—Interrupt Pin Register
(Audio—D31:F5)
Note: This register indicates which PCI interrupt pin is used for the AC'97 module interrupt.
The AC'97 interrupt is internally OR'd to the interrupt controller with the PIRQB# signal.
Table 477. Offset 3Dh: INTR_PN—Interrupt Pin Register (Audio—D31:F5)
31
Device:
3Dh
Offset:
3Dh
Default Value:
No
Lockable:
Bits Name
7:3 Reserved
2:0 AC'97 Interrupt Routing
13.1.19 Offset 40h: PCID—Programmable Codec ID
Register
(Audio—D31:F5)
Note: This register is used to specify the ID for the secondary and tertiary codecs for I/O
accesses. This register is not affected by the D3
Note: The value in this register must only be modified prior to any AC'97 codec accesses.
Table 478. Offset 40h: PCID—Programmable Codec ID Register (Audio—
D31:F5)
31
Device:
40h
Offset:
00h
Default Value:
No
Lockable:
Bits Name
7:4 Reserved
3:2 Tertiary Codec ID (TID)
Secondary Codec ID
1:0
(SCID)
November 2007
Order Number: 300641-004US
Attribute:
Power Well:
Description
Reserved.
Hardwired to 010b to select PIRQB#.
Attribute:
Power Well:
Description
Reserved.
These bits define the encoded ID that is used to address the
tertiary codec I/O space. Bit '1' is the first bit sent and Bit '0'
is the second bit sent on AC_SDATA_OUT during slot 0.
These two bits define the encoded ID that is used to address
the secondary codec I/O space. The two bits are the ID that
will be placed on slot 0, bits '0' and '1', upon an I/O access to
the secondary codec. Bit '1' is the first bit sent and bit '0' is
the second bit sent on AC_SDATA_OUT during slot 0.
5
Function:
Read-Only
8-bit
Size:
Core
to D0 transition.
HOT
5
Function:
Read/Write
8-bit
Size:
Core
Intel
Access
RO
Access
R/W
R/W
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6300ESB I/O Controller Hub
DS
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