Dma_Wrmsk-Dma Write All Mask Register; Timer I/O Registers - Intel 6300ESB Datasheet

®
8—Intel 6300ESB ICH
8.2.11 DMA_WRMSK—DMA Write All Mask Register
Table 230. DMA_WRMSK—DMA Write All Mask Register
I
31
Device:
Ch. #0-3 = 0Fh;
I/O Address:
Ch. #4-7 = DEh
0000 1111
Default Value:
No
Lockable:
Bits Name
7:4 Reserved
3:0 Channel Mask Bits
8.3

Timer I/O Registers

Table 231. Timer I/O Registers
Port
40h
41h
42h
43h
November 2007
Order Number: 300641-004US
Reserved. Must be 0.
This register permits all four channels to be simultaneously
enabled/disabled instead of enabling/disabling each channel
individually, as is the case with the Mask Register - Write
Single Mask Bit. In addition, this register has a read path to
allow the status of the channel mask bits to be read. A
channel's mask bit is automatically set to 1 when the Current
Byte/Word Count Register reaches terminal count (unless the
channel is in auto-initialization mode).
Setting the bit(s) to a 1 disables the corresponding DREQ(s).
Setting the bit(s) to a 0 enables the corresponding DREQ(s).
Bits [3:0] are set to 1 upon part reset or Master Clear. When
read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask
status.
Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked
Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked
Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked
Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked
NOTE: Disabling channel 4 also disables channels 0-3 due to
the cascade of channel's 0 - 3 through channel 4.
Aliases Register Name/Function
Counter 0 Interval Time Status Byte
Format
50h
Counter 0 Counter Access Port Register
Counter 1 Interval Time Status Byte
Format
51h
Counter 1 Counter Access Port Register
Counter 2 Interval Time Status Byte
Format
52h
Counter 2 Counter Access Port Register
Timer Control Word Register
53h Timer Control Word Register Read Back
Counter Latch Command
0
Function:
Read/Write
Attribute:
8-bit
Size:
Core
Power Well:
Description
Default
Value
0XXXXXXXb
Undefined
0XXXXXXXb
Undefined
0XXXXXXXb
Undefined
Undefined
XXXXXXX0b
Intel
Access
R/W
Type
RO
R/W
RO
R/W
RO
R/W
WO
WO
X0h WO
®
6300ESB I/O Controller Hub
DS
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