Intel 6300ESB Datasheet page 753

®
20—Intel 6300ESB ICH
Table 682. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2) (Sheet 2 of 2)
31
Device:
4A-4Bh
Offset:
0000h
Default Value:
Bits Name
Primary Drive 1 Cycle
5:4
Time (PCT1)
3:2 Reserved
Primary Drive 0 Cycle
1:0
Time (PCT0)
November 2007
Order Number: 300641-004US
Attribute:
Description
For Ultra ATA mode, the setting of these bits determines the
minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these
bits.
PCB1 = 0 (33MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = '1' (66MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = '1' (133MHz clk)
01 = CT 3 clks, RP 16 clks
00 = Reserved
10 = Reserved
11 = Reserved
Reserved.
For Ultra ATA mode, the setting of these bits determines the
minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these
bits.
PCB1 = 0 (33MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = '1' (66MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = '1' (133MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
2
Function:
Read/Write
16-bit
Size:
Intel
Access
R/W
R/W
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6300ESB I/O Controller Hub
DS
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