Modem Control Register (Mcr) - Intel 6300ESB Datasheet

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19—Intel 6300ESB ICH
Table 646. Line Status Register (LSR) (Sheet 2 of 2)
Line Status Register
LSR
read-only
Bit Number
3
2
1
0

19.5.1.3.8 Modem Control Register (MCR)

This 8-bit register controls the interface with the modem or data set (or a peripheral
device emulating a modem). The contents of the Modem Control register are described
in Table 647.
November 2007
Order Number: 300641-004US
Address:
Reset State:
Access:
Bit Mnemonic
Framing Error: FE indicates that the received character did not
have a valid stop bit. FE is set to a logic '1' when the bit following
the last data bit or parity bit is detected as a logic '0' bit (spacing
level). If the Line Control register had been set for two stop bit
mode, the receiver does not check for a valid second stop bit. The
FE indicator is reset when the processor reads the Line Status
Register. The UART will resynchronize after a framing error. To do
FE
this it assumes that the framing error was due to the next start
bit, so it samples this "start" bit twice and then takes in the
"data". In FIFO mode, FE shows a framing error for the character
at the top of the FIFO, not for the most recently received
character.
0 = No Framing error
1 = Invalid stop bit has been detected.
Parity Error: PE indicates that the received data character does
not have the correct even or odd parity, as selected by the even
parity select bit. The PE is set to a logic '1' upon detection of a
parity error and is reset to a logic '0' when the processor reads
the Line Status register. In FIFO mode, PE shows a parity error
PE
for the character at the top of the FIFO, not the most recently
received character.
0 = No Parity error
1 = Parity error has occurred.
Overrun Error: In non-FIFO mode, OE indicates that data in the
receiver buffer register was not read by the processor before the
next character was transferred into the receiver buffer register,
thereby destroying the previous character. In FIFO mode, OE
indicates that all 16 bytes of the FIFO are full and the most
OE
recently received byte has been discarded. The OE indicator is set
to a logic '1' upon detection of an overrun condition and reset
when the processor reads the Line Status register.
0 = No data has been lost
1 = Received data has been lost.
Data Ready: Bit 0 is set to a logic '1' when a complete incoming
character has been received and transferred into the receiver
buffer register or the FIFO. In non-FIFO mode, DR is reset to '0'
when the receive buffer is read. In FIFO mode, DR is reset to a
DR
logic '0' if the FIFO is empty (last character has been read from
RBR) or the RESETRF bit is set in FCR.
0 = No data has been received.
1 = Data is available in RBR or the FIFO.
Base + 05H
60H
8-bit
Function
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Intel 6300ESB I/O Controller Hub
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