Offset F0H: Fwh_Dec_En2—Fwh Decode Enable 2 Register (Lpc I/F—D31:F0) - Intel 6300ESB Datasheet

8.1.35 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2
Register (LPC I/F—D31:F0)
Note: This register determines which memory ranges will be decoded on the PCI bus and
forwarded to the FWH. The Intel
unless POS_DEC_EN is set to 1.
Table 215. Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—
D31:F0)
31
Device:
F0h
Offset:
0Fh
Default Value:
No
Lockable:
Bits Name
7:4 Reserved
3 FWH_70_EN
2 FWH_60_EN
1 FWH_50_EN
0 FWH_40_EN
®
Intel 6300ESB I/O Controller Hub
DS
342
®
6300ESB ICH will subtractively decode cycles on PCI
Attribute:
Power Well:
Description
Reserved.
Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FF70 0000h - FF7F FFFFh
FF30 0000h - FF3F FFFFh
Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FF60 0000h - FF6F FFFFh
FF20 0000h - FF2F FFFFh
Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FF50 0000h - FF5F FFFFh
FF10 0000h - FF1F FFFFh
Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FF40 0000h - FF4F FFFFh
FF00 0000h - FF0F FFFFh
0
Function:
Read/Write
8-bit
Size:
Core
Order Number: 300641-004US
®
Intel 6300ESB ICH—8
Access
R/W
R/W
R/W
R/W
November 2007