Interrupt Identification Register Decode; Fifo Control Register (Fcr) - Intel 6300ESB Datasheet

Table 643. Interrupt Identification Register Decode
Interrupt
ID bits
3 2 1 0
0 0 0 1 -
0 1 1 0
0 1 0 0
1 1 0 0
0 0 1 0
0 0 0 0

19.5.1.3.5 FIFO Control Register (FCR)

FCR is a write only register that is located at the same address as the IIR (IIR is a read
only register). FCR enables/disables the transmitter/receiver FIFOs, clears the
transmitter/receiver FIFOs, and sets the receiver FIFO trigger level.
Note: The use of bit 6 and 7 is different from the register definition of standard 16550.
Table 644. FIFO Control Register (FCR) (Sheet 1 of 2)
FIFO Control Register
FCR
write-only
Bit
Number
7:6
®
Intel 6300ESB I/O Controller Hub
DS
714
Interrupt SET/RESET Function
Priority Type
None No Interrupt is pending.
Highes
Receiver Overrun Error, Parity Error,
t
Line Status Framing Error, Break Interrupt.
Secon
Received
d
Non-FIFO mode: Receive
Data
Highes
Buffer is full.
Available.
t
FIFO mode: Trigger level
was reached.
Secon
FIFO Mode only: At least one
Character
d
character is in receiver FIFO
Timeout
Highes
and there was no activity for a
indication.
t
time period.
Third
Transmit
Non-FIFO mode: Transmit
Highes
FIFO Data
Holding Register Empty
t
Request
FIFO mode: Transmit FIFO
has half or less than half
data.
Fourth Clear to Send, Data Set
Modem
Highes Ready, Ring Indicator,
Status
t Received Line Signal Detect
Address:
Reset State:
Access:
Bit Mnemonic
Interrupt Trigger Level: When the number of bytes in the
receiver FIFO equals the interrupt trigger level programmed into
this field and the Received Data Available Interrupt is enabled
(through IER), an interrupt is generated and appropriate bits are
set in the IIR.
ITL[1:0]
00 = 1 byte or more in FIFO causes interrupt (same as 16550).
01 = RSVD
10 = 8 bytes or more in FIFO causes interrupt and DMA request
(same as 16550).
11 = RSVD
Source
-
Reading the Line Status Register.
Non-FIFO mode: Reading the
Receiver Buffer Register.
FIFO mode: Reading bytes until
Receiver FIFO drops below trigger
level or setting RESETRF bit in FCR
register.
Reading the Receiver FIFO or
setting RESETRF bit in FCR register.
Reading the IIR Register (if the
source of the interrupt) or writing into
the Transmit Holding Register.
Reading the IIR Register (if the
source of the interrupt) or writing to
the Transmitter FIFO.
Reading the modem status
register
Base + 02H
00H
8-bit
Function
Order Number: 300641-004US
®
Intel 6300ESB ICH—19
RESET Control
November 2007