Data Transfers To/From Main Memory - Intel 6300ESB Datasheet

Table 93. Queue Element Link Pointer (Sheet 2 of 2)
Bit
3:2 Reserved.
QH/TD Select (Q): This bit indicates to the hardware whether the item referenced by
the link pointer is another TD or a QH. For entries in a queue, this bit is typically set to
zero.
1
0 = TD
1 = QH
Terminate (T): This bit indicates to the Intel
in this queue. When HCD has new queue entries it overwrites this value with a new TD
pointer to the queue entry.
0
0 = Pointer is valid.
1 = Terminate (No valid queue entries).
5.17.3

Data Transfers to/from Main Memory

The following sections describe the details on how HCD and the Intel
communicate through the schedule data structures. The discussion is organized in a
top-down manner, beginning with the basics of walking the Frame List, followed by a
description of generic processing steps common to all transfer descriptors, and finally a
discussion on Transfer Queuing.
5.17.3.1 Executing the Schedule
Software programs the Intel
and the Frame List index, then causes the Intel
by setting the Run/Stop bit in the Control register to Run. The Intel
processes the schedule one entry at a time; the next element in the frame list is not
fetched until the current element in the frame list is retired.
Schedule execution proceeds in the following fashion:
1. The Intel
three fields. Bit 0 indicates whether the address pointer field is valid. Bit 1 indicates
whether the address points to a Transfer Descriptor or to a queue head. The third
field is the pointer itself.
2. When isochronous traffic is to be moved in a given frame, the Frame List entry
points to a Transfer Descriptor. When no isochronous data is to be moved in that
frame, the entry points to a queue head or the entry is marked invalid and no
transfers are initiated in that frame.
3. When the Frame List entry indicates that it points to a Transfer Descriptor, the
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Intel
initiate a transaction on USB. Each TD contains a link field that points to the next
entry, as well as indicating whether it is a TD or a QH.
4. When the Frame List entry contains a pointer to a QH, the Intel
processes the information from the QH to determine the address of the next data
object that it should process.
5. The TD/QH process continues until the millisecond allotted to the current frame
expires. At this point, the Intel
Frame List. When the Intel
descriptors during a given frame, those descriptors are retired by software without
having been executed.
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Intel 6300ESB I/O Controller Hub
DS
202
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6300ESB ICH with the starting address of the Frame List
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6300ESB ICH first fetches an entry from the Frame List. This entry has
6300ESB ICH fetches the entry and begins the operations necessary to
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6300ESB ICH is not able to process all of the transfer
Description
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6300ESB ICH that there are no valid TDs
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6300ESB ICH to execute the schedule
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6300ESB ICH fetches the next entry from the
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Intel 6300ESB ICH—5
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6300ESB ICH
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6300ESB ICH
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6300ESB ICH
November 2007
Order Number: 300641-004US