Configuration Space Register Summary; Device 28 – Hub Interface To Pci-X Bridge - Intel 6300ESB Datasheet

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18—Intel 6300ESB ICH
18.6 Device 28 – Hub Interface to PCI-X Bridge
18.6.1 Configuration Space Registers
18.6.1.1 Register Summary
Table 584. Configuration Space Register Summary (Sheet 1 of 2)
Start
00
04
06
08
09
0C
0D
0E
18
1B
1C
1E
20
24
28
2C
30
34
3C
3E
40
42
44
50
51
52
54
58
NOTE: Refer to the Intel
date value of the Revision ID register.
November 2007
Order Number: 300641-004US
End Symbol
03 ID
05 CMD
07 PSTS
08 RID
0B CC
0C CLS
0D PLT
0E HTYPE
1A BNUM
1B SLT
1D IOBL
1F SSTS
23 MBL
27 PMBL
2B PMBU32
2F PMLU32
33 IOBLU16
34 CAPP
3D INTR
3F BCTRL
41 CNF
42 MTT
47 STRP
50 PX_CAPID
51 PX_NXTP
53 PX_SSTS
57 PX_BSTS
5B PX_USTC
®
6300ESB I/O Controller Hub Specification Update for the most up-to-
Full Name
Identifiers
Command
Primary Status
Revision ID
Class Code
Cache Line Size
Primary Latency Timer
Header Type
Bus Numbers
Secondary Latency Timer
I/O Base and Limit
Secondary Status
Memory Base and Limit
Prefetchable Memory Base and Limit
Prefetchable Memory Base Upper 32
Bits
Prefetchable Memory Limit Upper 32
Bits
I/O Base and Limit Upper 16 Bits
Capabilities List Pointer
Interrupt Information
Bridge Control
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Intel 6300ESB ICH Configuration
Multi-Transaction Timer
PCI Strap Status
PCI-X Capabilities Identifier
Next Item Pointer
PCI-X Secondary Status
PCI-X Bridge Status
PCI-X Upstream Split Transaction
Control
Default
25AE8086h
0000h
0030h
See NOTE:
060400h
00h
00h
01h
000000h
00h
0000h
02A0h
00000000h
00010001h
00000000h
00000000h
00000000h
50h
0000h
0000h
000SSh
00h
00h
07h
00h
0001h
000100D0h
0000FFFFh
®
Intel 6300ESB I/O Controller Hub
DS
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